Esr - Exception Syndrome Register - IBM A2 User Manual

14.5.31 ESR - Exception Syndrome Register

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32:35 ///
36 PIL
37 PPR
38 PTR
39 FP
40 ST
41 ///
42 DLK0
43 DLK1
44 AP
45 PUO
46 BO
47 PIE
48 ///
49 UCT
50:52 ///
53 DATA
Version 1.3
October 23, 2012
ESR
62
0x0000000000000000
N
GESR
Initial
Value
0b0000 Reserved
0b0 Illegal Instruction Exception
1 Indicates an illegal instruction exception.
0b0 Privileged Instruction Exception
1 Indicates a privileged instruction exception.
0b0 Trap Exception
1 Indicates a trap exception.
0b0 Floating-Point Operation
1 Indicates floating-point operation.
0b0 Store Operation
1 Indicates store operation.
0b0 Reserved
0b0 Data Locking Exception 0
1 Indicates a dcbtls, dcbtstls, or dcblc instruction was executed with MSR[PR] = 1
and MSR[UCLE] = 0.
0b0 Data Locking Exception 1
1 Indicates an icbtls or icblc instruction was executed MSR[PR] = 1 and
MSR[UCLE] = 0.
0b0 Auxiliary Processor Operation
1 Indicates auxiliary processor operation.
0b0 Unimplemented Operation Exception
1 Indicates an unimplemented operation exception.
0b0 Byte Ordering Exception
1 Indicates a byte ordering exception.
0b0 Imprecise Exception
1 Indicates an imprecise exception.
0b0 Reserved
0b0 Unavailable Coprocessor Type
1 Indicates that execution of an icswx instruction was attempted that specified a
coprocessor type that was marked as unavailable.
0b000 Reserved
0b0 Data Access
1 Indicates if the interrupt is due to an LRAT miss resulting from a page table trans-
lation of a load, store, or cache management operand address.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Priv
Priv
Y
func
Alphabetical Register Listing
Page 579 of 897