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User's Manual
A2 Processor
When underflow exception is disabled (FPSCR[UE] = 0) and underflow occurs, the following actions are
taken:
• The Underflow Exception bit is set.
FPSCR[UX] 1
• FPR(FRT) rounded result
• FPSCR[FPRF] class and sign of the result (Normalized Number, Denormalized Number, or Zero)
8.4.5 Inexact Exception
An inexact exception occurs when either of the following conditions occur during rounding:
• The rounded result differs from the intermediate result, assuming both the precision and the exponent
range of the intermediate result to be unbounded. In this case, the result is said to be inexact. If the
rounding causes an enabled overflow exception or an enabled underflow exception, an inexact exception
also occurs only if the significands of the rounded result and the intermediate result differ.)
• The rounded result overflows and overflow exception is disabled.
8.4.5.1 Action
The action to be taken does not depend on the setting of FPSCR[XX].
When an inexact exception occurs, the following actions are taken:
• The Inexact Exception bit is set.
FPSCR[XX] 1
• FPR(FRT) rounded or overflowed result
• FPSCR[FPRF] class and sign of the result
Programming Note: In some implementations, enabling inexact exceptions might degrade
performance more than does enabling other types of floating-point exception.
8.5 Exception Priorities for Floating-Point Load and Store Instructions
The following prioritized list of exceptions can occur as a result of the attempted execution of any floating-
point load and store instruction.
1. Debug (instruction address compare)
2. Instruction TLB error (all types)
3. Instruction storage interrupt (all types)
4. Program (illegal instruction)
5. Floating-point unavailable
6. Program (unimplemented operation)
7. Data TLB error (all types)
8. Data storage (all types)
FU Interrupts and Exceptions
Page 380 of 864
Version 1.3
October 23, 2012
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