The A2 Core As A Power Isa Implementation; Embedded Hypervisor; A2 Core Organization - IBM A2 User Manual

1.3 The A2 Core as a Power ISA Implementation

The A2 core implements the full, 64-bit fixed-point Power ISA Architecture. The A2 core fully complies with
these architectural specifications. The core does not implement the floating-point operations, although a
floating-point unit (FU) can be attached (using the AXU interface).

1.3.1 Embedded Hypervisor

The A2 core implements the Embedded Hypervisor Architecture to provide secure compute domains and
operating system virtualization. The Embedded Hypervisor Architecture introduces the concept of partitions
by two main architectural changes. The first is by extending the virtual address with a logical partition identi-
fier (LPID). The identifier serves an analogous purpose to the process ID (PID) and is used to distinguish
partitions. The second change is introducing a new privilege level above supervisor and reallocating owner-
ship of resources between the two levels. Moving the ownership of certain resources beyond the supervisor
helps software to provide secure compute domains.
In addition to providing logical partitions, the following requirements are set forth:
• Ensure a secure environment. An operating system in one logical partition is not allowed to affect the
resources of an operating system in another partition.
• Maintain compatibility with the existing programming model. An existing operating system today should
require only minor initialization changes to run.
• An operating system running in a logical partition should not be able to deny service to any shared
resources.
• Clean and secure communication channels between supervisor and embedded hypervisor states (in both
directions).
• The ability to run guest operating systems efficiently and provide real-time response to interrupts.

1.4 A2 Core Organization

The A2 core includes a concurrent-issue instruction fetch and decode unit with an attached branch unit,
together with a pipeline for complex integer, simple integer, and load/store operations. The A2 core also
includes a memory management unit (MMU); separate instruction and data cache units; pervasive and debug
logic; and timer facilities.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Overview
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