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User's Manual
A2 Processor
Engineering Note: The TLB0CFG[PT] and [IND] bits are both resident on the boot configuration scan chain.
Therefore, it is possible to set these bits independently. For A2, because there is only one shared TLB physi-
cally resident on this processor, it is recommended that both of these bits be set to the same value (0b00 for
software table walking only or 0b11 to support hardware table walking). Setting IND = 0 and PT = 1 has a
similar effect as setting both bits low (that is, indirect entries are assumed to not be supported; therefore, no
hardware table walking occurs). Setting IND = 1 and PT = 0 has the effect of allowing indirect entry recogni-
tion, and hardware table walking can occur. However, when the subsequent attempt to write the page table
entry into the TLB occurs, the results depend on the page table entry valid bit setting. When PTE.V = 1 in this
mode, it is deemed as a valid attempt to write a TLB entry and a TLB ineligible exception occurs because PT
= 0. When PTE.V = 0, it is not deemed as a valid attempt to write a TLB entry; therefore, no exception occurs
as the result of PT = 0. In either of these cases, no TLB entry is written.
Version 1.3
Memory Management
October 23, 2012
Page 267 of 864
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