Iac Debug Event Fields - IBM A2 User Manual

10.4.1.1 IAC Debug Event Fields

Several fields in DBCR0 and DBCR1 are used to specify the IAC conditions, as follows:
IAC Event Enable Field
DBCR0[IAC1, IAC2, IAC3, IAC4] are the individual IAC event enables for each of the four IAC events:
IAC1, IAC2, IAC3, and IAC4. For a given IAC event to occur, the corresponding IAC event enable bit in
DBCR0 must be set. When a given IAC event occurs, the corresponding DBSR[IAC1, IAC2, IAC3, IAC4]
bit is set.
IAC Mode Field
DBCR1[IAC12M, IAC34M] control the comparison mode for the IAC1/IAC2 and IAC3/IAC4 events,
respectively. There are two comparison modes supported by the A2 core:
• Exact comparison mode (DBCR1[IAC12M/IAC34M] = 0b0)
In this mode, the instruction address is compared to the value in the corresponding IAC register; the
IAC event occurs only if the comparison is an exact match. When the processor is operating in 32-bit
mode (MSR[CM] = 0), the addresses are masked to compare only bits 32 through 63.
• Address bit match mode (DBCR1[IAC12M/IAC34M] = 0b1)
In this mode, the IAC1 or IAC2 event occurs only if the instruction address matches the value in the
IAC1 register, as masked by the value in the IAC2 register. That is, the IAC1 register specifies an
address value, and the IAC2 register specifies an address bit mask that determines which bit of the
instruction address should participate in the comparison to the IAC1 value. For every bit set to 1 in
the IAC2 register, the corresponding instruction address bit must match the value of the same bit
position in the IAC1 register. For every bit set to 0 in the IAC2 register, the corresponding address bit
comparison does not affect the result of the IAC event determination. Similarly, instruction address
matches for IAC3 and IAC4 events occur as described previously for IAC1 and IAC2. When the pro-
cessor is operating in 32-bit mode (MSR[CM] = 0), the addresses are masked to compare only bits
32 through 63.
When the instruction address matches the address bit mask mode conditions, either one or both of
the IAC debug event bits is set in the DBSR, as determined by which IAC event enable bits are set in
DBCR0. That is, when an address bit mask mode IAC debug event occurs, the setting of
DBCR0[IAC1, IAC2] determines whether one or the other or both of the DBSR[IAC1, IAC2] bits are
set. In like manner, the setting of DBCR0[IAC3, IAC4] determines how the DBSR[IAC3, IAC4] bits
are set. It is a programming error to set the IAC mode field to address bit mask mode for IAC12M or
IAC34M without also enabling at least one of the paired IAC event enable bits in DBCR0 (IAC1/IAC2
or IAC3/IAC4 respectively).
• The A2 core does not support the IAC range inclusive comparison mode.
• The A2 core does not support the IAC range exclusive comparison mode.
IAC User/Supervisor Field
DBCR1[IAC1US, IAC2US, IAC3US, IAC4US] are the individual IAC user/supervisor fields for each of the
four IAC events. The IAC user/supervisor fields specify the operating mode of the processor in order for
the corresponding IAC event to occur. The operating mode is determined by the Problem State field of
the Machine State Register (MSR[PR]; see Section 2.4.2.4 Machine State Register on page 85). When
the IAC user/supervisor field is 0b00, the operating mode does not matter; the IAC debug event can
occur independent of the state of MSR[PR]. When this field is 0b10, the processor must be operating in
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Debug Facilities
Page 403 of 864