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• Certain forms of various integer instructions (the "." forms) implicitly update CR[CR0], as do certain forms
of the auxiliary processor instructions implemented within the A2 core.
• Auxiliary processor instructions can, in general update, a specified CR field in an implementation-speci-
fied manner. In addition, if an auxiliary processor implements the floating-point operations specified by
the Power ISA, those instructions update the CR in the manner defined by the architecture. See
Book III-E: Power ISA Architecture Enhanced for Embedded Applications for details.
CR[CR0] Implicit Update By Integer Instructions
Most of the CR-updating instructions listed in Table 2-36 implicitly update the CR0 field. These are the
various "dot-form" instructions, indicated by a "." in the instruction mnemonic. Most of these instructions
update CR[CR0] according to an arithmetic comparison of 0 with the 64-bit result in 64-bit mode or compar-
ison with the lower 32 bits of the result in 32-bit mode. The compare to 0 uses a signed comparison, indepen-
dent of whether the actual operation being performed by the instruction is considered "signed" or not. For
example, logical instructions such as and., or., and nor. update CR[CR0] according to this signed compar-
ison to 0, even though the result of such a logical operation is not typically interpreted as a signed value. For
each of these dot-form instructions, the individual bits in CR[CR0] are updated as follows:
CR[CR0]
— LT
0
CR[CR0]
— GT
1
CR[CR0]
— EQ
2
CR[CR0]
— SO
3
Note that if an arithmetic overflow occurs, the "sign" of an instruction result indicated in CR[CR0] might not
represent the "true" (infinitely precise) algebraic result of the instruction that set CR0. For example, if an add.
instruction adds two large positive numbers and the magnitude of the result cannot be represented as a twos-
complement number in a 64-bit register in 64-bit mode or in a 32-bit register in 32-bit mode, an overflow
occurs and CR[CR0]
is set, even though the infinitely precise result of the add is positive.
0
Similarly, adding the largest 64-bit twos-complement negative number (0x8000_0000_0000_0000) to itself in
64-bit mode or the largest 32-bit twos-complement negative number (0x8000_0000) to itself in 32-bit mode
results in an arithmetic overflow and 0x0000_0000_0000_0000 in 64-bit mode or 0x0000_0000 (in bits 32:63)
in 32-bit mode is recorded in the target register. CR[CR0]
precise result is negative.
CR[CR0]
is a copy of XER[SO] at the completion of the instruction, whether or not the instruction that is
3
updating CR[CR0] is also updating XER[SO]. Note that if an instruction causes an arithmetic overflow but is
not of the form that actually updates XER[SO], then the value placed in CR[CR0]
metic overflow that occurred on the instruction (it is merely a copy of the value of XER[SO] that was already in
the XER before the execution of the instruction updating CR[CR0]).
There are a few dot-form instructions that do not update CR[CR0] in the fashion described above. These
instructions are: stwcx., stdcx.
Version 1.3
October 23, 2012
Less than 0; set if the most-significant bit of the 64-bit result in 64-bit mode or
the most-significant bit of the 32-bit result in 32-bit mode is 1.
Greater than 0; set if the 64-bit result in 64-bit mode or the 32-bit result in
32-bit mode is nonzero and the most-significant bit of the result is 0.
Equal to 0; set if the 64-bit result in 64-bit mode or the 32-bit result in 32-bit
mode is 0.
Summary overflow; a copy of XER[SO] at the completion of the instruction
(including any XER[SO] update being performed the instruction itself.
is set, indicating a result of 0, but the infinitely
2
3
User's Manual
A2 Processor
does not reflect the arith-
CPU Programming Model
Page 109 of 864
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