Appendix A. Processor Instruction Summary; Instruction Formats; Implemented Instructions Sorted By Mnemonic - IBM A2 User Manual

Appendix A. Processor Instruction Summary

This appendix lists all of the A2 core instructions, summarized alphabetically by mnemonic. Extended
mnemonics are not included in the opcode list. Reserved-nop opcodes are included.
A.1 Instruction Formats
Instructions are 4 bytes long. Instruction addresses are always word aligned.
Instruction bits 0 through 5 always contain the primary opcode. Many instructions have an extended opcode
in another field. Remaining instruction bits contain additional fields. All instruction fields belong to one of the
following categories:
• Defined
These instructions contain values, such as opcodes, that cannot be altered. The instruction format dia-
grams specify the values of defined fields.
• Variable
These fields contain operands, such as GPR selectors and immediate values, that can vary from execu-
tion to execution. The instruction format diagrams specify the operands in the variable fields.
• Reserved
Bits in reserved fields should be set to 0. In the instruction format diagrams, /, //, or /// denotes a reserved
field, in a register, instruction, field, or bit string.
If any bit in a defined field does not contain the expected value, the instruction is illegal, and an illegal instruc-
tion exception occurs. If any bit in a reserved field does not contain 0, the instruction form is invalid; its result
is architecturally undefined. The A2 core executes all invalid instruction forms without causing an illegal
instruction exception.
A.2 Implemented Instructions Sorted by Mnemonic
The Form column in Table A-1 refers to the arrangement of valid field combinations within the 4-byte instruc-
tion. See the Power ISA, V 2.06B for a definition of the terms used in this column and the Category column.
In the Implemented column, "Y" indicates that the A2 core does implement this instruction. An "N" indicates
that this instruction is not implemented.
In the Microcoded column, "Y" indicates that the A2 implementation is via microcode.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Processor Instruction Summary
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