IBM A2 User Manual page 18

User's Manual
A2 Processor
14.5.115 TENC - Thread Enable Clear Register .......................................................................... 675
14.5.116 TENS - Thread Enable Set Register .............................................................................. 676
14.5.117 TENSR - Thread Enable Status Register ...................................................................... 677
14.5.118 TIR - Thread Identification Register ............................................................................... 678
14.5.119 TLB0CFG - TLB 0 Configuration Register ..................................................................... 679
14.5.120 TLB0PS - TLB 0 Page Size Register ............................................................................. 680
14.5.121 TRACE - Hardware Trace Macro Control Register ........................................................ 681
14.5.122 TSR - Timer Status Register .......................................................................................... 682
14.5.123 UDEC - User Decrementer ............................................................................................ 683
14.5.124 VRSAVE - Vector Register Save ................................................................................... 684
14.5.125 XER - Fixed Point Exception Register ........................................................................... 685
14.5.126 XESR1 - XU Event Select Register 1 ............................................................................ 686
14.5.127 XESR2 - XU Event Select Register 2 ............................................................................ 687
14.5.128 XESR3 - XU Event Select Register 3 ............................................................................ 688
14.5.129 XESR4 - XU Event Select Register 4 ............................................................................ 689
14.5.130 XUCR0 - Execution Unit Configuration Register 0 ......................................................... 690
14.5.131 XUCR1 - Execution Unit Configuration Register 1 ......................................................... 693
14.5.132 XUCR2 - Execution Unit Configuration Register 2 ......................................................... 694
14.5.133 XUCR3 - Execution Unit Configuration Register 3 ......................................................... 695
14.5.134 XUCR4 - Execution Unit Configuration Register 4 ......................................................... 696
14.5.135 XUDBG0 - Execution Unit Debug Register 0 ................................................................. 697
14.5.136 XUDBG1 - Execution Unit Debug Register 1 ................................................................. 698
14.5.137 XUDBG2 - Execution Unit Debug Register 2 ................................................................. 699
15. SCOM Accessible Registers ................................................................................. 701
15.1 Serial Communications (SCOM) Description .............................................................................. 701
15.2 SCOM Register Summary ........................................................................................................... 703
15.2.1 Read and Write Access Methods ....................................................................................... 703
15.2.1.1 Reset with AND Mask ................................................................................................. 703
15.2.1.2 Set with OR Mask ....................................................................................................... 703
15.2.2 SCOM Register Summary Table ....................................................................................... 703
15.3 Alphabetical Register Listing ....................................................................................................... 705
15.3.1 AXU Debug Select Register (ABDSR) ............................................................................... 705
15.3.2 Error Injection Register (ERRINJ) ...................................................................................... 706
15.3.3 Fault Isolation Register 0 and Associated Registers ......................................................... 707
15.3.4 Fault Isolation Register 1 and Associated Registers ......................................................... 711
15.3.5 Fault Isolation Register 2 and Associated Registers ......................................................... 716
15.3.6 IU Debug Select Register (IDSR) ...................................................................................... 720
15.3.7 MMU/PC Debug Select Register (MPDSR) ....................................................................... 723
15.3.8 PC Configuration Register 0 (PCCR0) ............................................................................... 725
15.3.9 Ram Data Registers (RAMD, RAMDH, RAMDL) ............................................................... 726
15.3.10 Ram Instruction and Command Registers (RAMC, RAMI, RAMIC) ................................ 727
15.3.11 Special Attention Register (SPATTN) .............................................................................. 729
15.3.12 Thread Control and Status Register (THRCTL) ............................................................... 730
15.3.13 XU Debug Select Register1 (XDSR1) .............................................................................. 731
15.3.14 XU Debug Select Register2 (XDSR2) .............................................................................. 734
Contents
Page 18 of 864
Version 1.3
October 23, 2012