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14.5.5 CCR2 - Core Configuration Register 2
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
32
EN_DCR
33
EN_TRACE
34
EN_PC
35:43
IFRATSC
44
IFRAT
45:53
DFRATSC
54
DFRAT
Version 1.3
October 23, 2012
CCR2
1010
0x0000000000000001
N
Initial
Value
0b0
Enable DCR instructions
0
Disable Embedded.Device Control category instructions.
1
Enable Embedded.Device Control category instructions.
0b0
Enable Hardware Trace Control Register
0
Writes to TRACE SPR behave as a nop.
1
Writes to TRACE SPR are enabled.
0b0
Enable Processor Control Instructions
0
Disable msgsnd and msgclr instructions; causes an illegal instruction type
gram interrupt.
1
Enable msgsnd and msgclr instructions.
0x0
IFRAT Storage Control
Sets the storage control bits used when CCR2[IFRAT] = 1. When set to 1, indicates:
0
(W) Write through required
1
(I) Caching inhibited
2
(M) Memory coherence required
3
(G) Guarded
4
(E) Big endian
5
(U0) User defined bit 0
6
(U1) User defined bit 1
7
(U2) User defined bit 2
8
(U3) User defined bit 3
0b0
Instruction Force Real Address Translation
Debug facility that forces EA = RA address translation for instructions:
0
Access I-ERAT for instruction translation.
1
Force EA = RA instruction translation.
0x0
DFRAT Storage Control
Sets the storage control bits used when CCR2[DFRAT] = 1. When set to 1, indicates:
0
(W) Write through required
1
(I) Caching inhibited
2
(M) Memory coherence required
3
(G) Guarded
4
(E) Big endian
5
(U0) User defined bit 0
6
(U1) User defined bit 1
7
(U2) User defined bit 2
8
(U3) User defined bit 3
0b0
Data Force Real Address Translation
Debug facility that forces EA = RA address translation for data:
0
Access D-ERAT for data translation.
1
Force EA = RA data translation.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
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A2 Processor
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