Register Management Instructions; System Linkage Instructions; Processor Control Instructions; Storage Control Instructions - IBM A2 User Manual

2.8.3.2 Register Management Instructions

These instructions move data between the GPRs and control registers in the A2 core.
Table 2-22 lists the register management instructions in the A2 core.

Table 2-22. Register Management Instructions

CR
mcrf mfdcr
mcrxr mfdcrx
mfcr mfdcrux
mfocrf mtdcr
mtcrf mtdcrx
mtocrf mtdcrux
1. When CCR2(EN_DCR) is zero, DCR instructions are dropped silently. They are no-ops and do not cause an exception.

2.8.3.3 System Linkage Instructions

These instructions invoke supervisor software level for system services and return from interrupts.
When executing in the guest state (MSR[GS,PR] = 0b10), execution of an rfi instruction is mapped to rfgi
and the rfgi instruction is executed in place of the rfi.
Table 2-23 lists the system linkage instructions in the A2 core.

Table 2-23. System Linkage Instructions

ehpriv
rfi
rfci
rfgi
rfmci
sc

2.8.3.4 Processor Control Instructions

The msgsnd and msgclr instructions are provided for sending and clearing messages to processors and
other devices in the coherence domain. These instructions are hypervisor privileged.
Table 2-28 shows the processor control instructions in the A2 core.

Table 2-24. Processor Control Instruction

msgsnd
msgclr

2.8.4 Storage Control Instructions

These instructions manage the instruction and data caches and the TLB of the A2 core. Instructions are also
provided to synchronize and order storage accesses. The instructions in these three subcategories of storage
control instructions are described in the following sections.
Version 1.3
October 23, 2012
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DCR MSR
mfmsr
mtmsr
wrtee
wrteei
SPR
mfspr
mttb
mtspr
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