Timer Status Register (Tsr); Freezing The Timer Facilities - IBM A2 User Manual

9.7 Timer Status Register (TSR)

The TSR is a privileged SPR that records the status of DEC, UDEC, FIT, and watchdog timer events. The
fields of the TSR are generally set to 1 only by hardware and cleared to 0 only by software. Hardware cannot
clear any fields in the TSR, nor can software set any fields. Software can read the TSR into a GPR using
mfspr. Clearing the TSR is performed using mtspr by placing a 1 in the GPR source register in all bit posi-
tions that are to be cleared in the TSR, and a 0 in all other bit positions. The data written from the GPR to the
TSR is not direct data, but a mask. A 1 clears the bit and a 0 leaves the corresponding TSR bit unchanged.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32 ENW
33 WIS
34:35 WRS
36 DIS
37 FIS
38 UDIS
39:63 ///

9.8 Freezing the Timer Facilities

The debug mechanism provides a means for temporarily "freezing" the timers upon a debug exception.
Specifically, the time base and decrementer can be prevented from incrementing and decrementing, respec-
tively, whenever a debug exception is recorded in the Debug Status Register (DBSR). This allows a debugger
to simulate the appearance of real time, even though the application has been temporarily halted to service
the debug event.
See Debug Facilities on page 399 for more information about freezing the timers.
Version 1.3
October 23, 2012
TSR
336
0x0000000000000000
N
Initial
Value
0b0 Enable Next Watchdog Timer
0 Action taken on the next watchdog timer exception will be to set TSR{ENW].
1 Action taken on the next watchdog timer exception is governed by TSR[WIS].
0b0 Watchdog Timer Interrupt Status
0 A watchdog timer event has not occurred.
1 A watchdog timer event has occurred. When (MSR[CE] = 1 or MSR[GS] = 1) and
TCR[WIE] = 1, a watchdog timer interrupt is taken.
0b00 Watchdog Timer Reset Status
00 No reset: No watchdog timer reset has occurred.
01 Reset1: A watchdog timer initiated Reset1 reset occurred.
10 Reset2: A watchdog timer initiated Reset2 reset occurred.
11 Reset3: A watchdog timer initiated Reset3 reset occurred
0b0 Decrementer Interrupt Status
A decrementer event has occurred.
0b0 Fixed-Interval Timer Interrupt Status
A fixed-interval timer event has occurred.
0b0 User Decrementer Interrupt Status
A user decrementer event has occurred.
0x0 Reserved
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
WC,AM
func
Timer Facilities
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