Lsu Event Select Registers - IBM A2 User Manual

User's Manual
A2 Processor

11.5.4 LSU Event Select Registers

Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
32 INPSELEB0
33:37 MUXSELEB0
38 INPSELEB1
39:43 MUXSELEB1
44 INPSELEB2
45:49 MUXSELEB2
50 INPSELEB3
51:55 MUXSELEB3
56:63 ///
Performance Events and Event Selection
Page 472 of 864
XESR3
920
0x0000000000000000
Y
Initial
Value
0b0 Multiplexer Event_Bits[0] Input Select
For event multiplexer, bit 0, determines which group of performance event inputs are
selected to drive the bank of 2:1 multiplexers.
0 T0_Events[0:31]
1 T1_Events[0:31]
0x0 Multiplexer Event_Bits[0] 2:1 Multiplexer Select
Determines which 2:1 multiplexer is gated for driving event mux bit 0
(lsu_pc_event_bits[0]).
Decoded values select multiplexer 0 ('00000') through multiplexer 31 ('11111').
0b0 Multiplexer Event_Bits[1] Input Select
For event multiplexer, bit 1, determines which group of performance event inputs are
selected to drive the bank of 2:1 multiplexers.
0 T0_Events[0:31]
1 T1_Events[0:31]
0x0 Multiplexer Event_Bits[1] 2:1 Multiplexer Select
Determines which 2:1 multiplexer is gated for driving event multiplexer bit 1
(lsu_pc_event_bits[1]).
Decoded values select multiplexer 0 ('00000') through multiplexer 31 ('11111').
0b0 Multiplexer Event_Bits[2] Input Select
For event multiplexer, bit 2, determines which group of performance event inputs are
selected to drive the bank of 2:1 multiplexers.
0 T0_Events[0:31]
1 T1_Events[0:31]
0x0 Multiplexer Event_Bits[2] 2:1 Mux Select
Determines which 2:1 multiplexer is gated for driving event multiplexer bit 2
(lsu_pc_event_bits[2]).
Decoded values select multiplexer 0 ('00000') through multiplexer 31 ('11111').
0b0 Multiplexer Event_Bits[3] Input Select
For event multiplexer, bit 3, determines which group of performance event inputs are
selected to drive the bank of 2:1 multiplexers.
0 T0_Events[0:31]
1 T1_Events[0:31]
0x0 Multiplexer Event_Bits[3] 2:1 Multiplexer Select
Determines which 2:1 multiplexer is gated for driving event multiplexer bit 3
(lsu_pc_event_bits[3]).
Decoded values select multiplexer 0 ('00000') through multiplexer 31 ('11111').
0x0 Reserved
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Priv
Priv
N
func
Version 1.3
October 23, 2012