IBM A2 User Manual page 335

Execute Access Control Exception
An execute access control exception is caused by one of the following:
• While in user mode (MSR[PR] = 1), an instruction fetch attempts to access a location in storage that is not
enabled for execute access in user mode (that is, the TLB entry associated with the memory page being
accessed has UX = 0).
• While in supervisor mode (MSR[PR] = 0), an instruction fetch attempts to access a location in storage
that is not enabled for execute access in supervisor mode (that is, the TLB entry associated with the
memory page being accessed has SX = 0).
Architecture Note: The Power ISA defines an additional instruction storage exception, the byte ordering
exception. This exception is defined to assist implementations that cannot support dynamically switching byte
ordering between consecutive instruction fetches or cannot support a given byte order at all. The A2 core,
however, supports instruction fetching from both big-endian and little-endian memory pages, so this excep-
tion cannot occur.
Byte Ordering Exception
An instruction storage byte ordering exception cannot occur in A2.
Page Table Fault Exception
A page table fault exception is caused when a page table translation occurs for a data access due to a load,
store, or cache management instruction and the page table entry that is accessed is invalid (PTE Valid
bit = 0).
TLB Ineligible Exception
A TLB ineligible exception is caused when a page table translation occurs for an instruction fetch and any of
the following conditions are true:
• The only TLB entries that can be used to hold the translation for the virtual address have IPROT = 1.
• No TLB array can be loaded from the page table for the page size specified by the PTE.
• The PTE[ARPN] is treated as an LPN, and there is no TLB array that meets all the following conditions:
– The TLB array supports the page size specified by the PTE.
– The TLB array can be loaded from the page table (TLB0CFG[PT] = 1).
An instruction storage interrupt resulting from a TLB ineligible exception is always directed to hypervisor state
regardless of the setting of EPCR[ISIGS].
When an instruction storage interrupt occurs, the processor suppresses the execution of the instruction
causing the instruction storage exception, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| 0x080.
If the interrupt is directed to the guest state (EPCR[ISIGS] = 1 and MSR[GS] = 1), GSRR0, GSRR1, and
GESR are set in place of SRR0, SRR1, and ESR respectively, and instruction execution resumes at address
GIVPR[IVP] || 0x080.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
CPU Interrupts and Exceptions
Page 335 of 864