Xu Performance Events Table; Table 11-5. Xu Performance Events Table - IBM A2 User Manual

User's Manual
A2 Processor
Table 11-4. IU Performance Events Table
(Use IESR1 and IESR2 for corresponding multiplexer selects)
Note: See the unit performance events table column descriptions in Section 11.3.3 on page 457.
Event Name
(Tag: B/C/E/S/V)
FXU Issue Priority Loss (C)
Reserved
FXU Issue Cycle Count (C)
Total Issue Cycle Count (C)
Instruction Match Count (C)
Reserved

11.4.3 XU Performance Events Table

Table 11-5. XU Performance Events Table

(Use XESR1 and XESR2 for corresponding multiplexer selects)
Note: See the unit performance events table column descriptions in Section 11.3.3 on page 457.
Event Name
(Tag: B/C/E/S/V)
Processor Busy (C)
Branch Commit (C)
Branch Mispredict Commit
(S)
Branch Target Address
Mispredict Commit (S)
Thread Running (C)
Timebase Tick (C)
SPR Read Commit (C)
SPR Write Commit (C)
Cycles stalled on waitrsv (B) Number of cycles between commit of waitrsv and wakeup by
External Interrupt Asserted
(C)
Critical External Interrupt
Asserted (C)
Performance Monitor
Interrupt Asserted (C)
PPC Commit (C)
Performance Events and Event Selection
Page 460 of 864
(Sheet 3 of 3)
Description
Cycle count for FXU instruction that is valid in issue and
another thread issues because it has priority (see IS2 Stall for
combined AXU/FXU issue priority loss).
Reserved.
Cycle count for FXU instructions issued per thread.
AXU Issue Cycle Count = Total Issue Cycle Count minus FXU
Issue Cycle Count.
Cycle count for all instructions issued per thread.
Cycle count for instruction matches issued per thread.
(Sheet 1 of 2)
Description
Cycles that any thread is running.
Number of branches committed.
Number of mispredicted branches committed (does not include
target address mispredicted).
Number of branch target addresses mispredicted committed.
Number of cycles that thread is in run state.
Number of times the time base has incremented.
Number of mfspr, mftb, mfmsr, or mfcr instructions commit-
ted.
Number of mtspr, mtmsr, mtcrf, wrtee, or wrteei instructions
committed.
lost reservation.
Number of cycles the external interrupt signal is asserted.
Number of cycles the critical external interrupt signal is
asserted.
Number of cycles the performance monitor interrupt signal is
asserted.
Number of instructions committed. Microcode sequences count
as one instruction.
Per Input_Sel Mux_Sel
Core Options Decode
Event? (Tx_Events) (Mux 0:31)
No any
No any
No any
No any
any
Per Input_Sel Mux_Sel
Core Options Decode
Event? (Tx_Events) (Mux 0:31)
Yes 0
Yes 1
Yes 2
Yes 3
No any
No any
No any
No any
No any
No any
No any
No any
No any
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