IBM A2 User Manual page 771

Table C-4. IU Debug Mux1 Debug and Trigger Groups
Debug Group
5 (0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33:37) <= iuq_slice0.dep0.is2_ta(1 to 5);
(38:75) same as 0:37, except for iuq_slice1
(76:87) <= tidn
Version 1.3
October 23, 2012
<= iuq_slice0.dec0.is1_instr_v
<= iuq_slice0.dec0.is1_frt_v
<= iuq_slice0.dec0.is1_fra_v
<= iuq_slice0.dec0.is1_frb_v
<= iuq_slice0.dec0.is1_frc_v
<= iuq_slice0.dec0.is1_ldst
<= iuq_slice0.dec0.is1_st
<= iuq_slice0.dec0.is1_cr_setter
<= iuq_slice0.dec0.is1_cr_writer
<= iuq_slice0.dec0.is1_is_ucode
<= iuq_slice0.dec0.is1_to_ucode
<= iuq_slice0.dec0.is1_frt_buf(1)
<= iuq_slice0.dec0.is1_fmul_uc
<= iuq_slice0.dec0.is1_in_divsqrt_mode_or1d;
<= iuq_slice0.dep0.is1_dep_hit_db
<= iuq_slice0.dep0.is1_raw_hit_db
<= iuq_slice0.dep0.raw_fra_hit_db
<= iuq_slice0.dep0.raw_frb_hit_db
<= iuq_slice0.dep0.raw_frc_hit_db
<= iuq_slice0.dep0.is1_prebubble_skip_db
<= iuq_slice0.dep0.raw_cr_hit_db
<= iuq_slice0.dep0.bubble3_is1_db
<= iuq_slice0.dep0.is1_lmq_waw_hit_db
<= iuq_slice0.dep0.is1_waw_load_hit_db
<= iuq_slice0.dep0.iu_au_is1_hold_db
<= iuq_slice0.dep0.iu_au_is2_stall_db
<= iuq_slice0.dep0.iu_au_is1_flush_db
<= iuq_slice0.dep0.iu_au_is2_flush_db
<= iuq_slice0.dep0.iu_au_rf0_flush_db
<= iuq_slice0.dep0.is1_instr_v_din_db
<= iuq_slice0.dep0.is2_instr_v
<= iuq_slice0.dep0.rf0_instr_v
<= iuq_slice0.dep0.rf1_instr_v
(Sheet 4 of 6)
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User's Manual
A2 Processor
Debug and Trigger Groups
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