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User's Manual
A2 Processor
10.4.9 Unconditional Debug Event (UDE)
UDE debug events occur when a debug tool asserts the unconditional debug event request via the SCOM-
accessible THRCTL[UDE] bit. The UDE debug event is the only event that does not have a corresponding
enable field in either DBCR0 or DBCR3.
The occurrence of a UDE debug event is recorded in DBSR[UDE]. If debug interrupts are not enabled
(MSR[DE] = 0), the imprecise debug event (DBSR[IDE]) bit is also set. The resulting actions taken by the
processor due to the UDE debug event depend on the specific debug configuration.
When operating in external debug mode (DBCR0[EDM] = 1), the setting of PCCR0[DBA] determines the
resulting debug actions. If the debug action is a stop, the processor enters the stop state and ceases the
processing of instructions. The program counter contains the address of the instruction that would have
executed next, had the UDE debug event not occurred. If the PCCR0[DBA] decode does not stop the
processor, instruction execution continues, and any additional debug actions are determined by the setting of
DBCR0[IDM].
When operating in internal debug mode (DBCR0[IDM] = 1) with debug interrupts enabled (MSR[DE] = 1), a
Debug interrupt occurs with CSRR0 set to the address of the instruction that would have executed next, had
the UDE debug event not occurred. When operating in internal debug mode with debug interrupts disabled
(MSR[DE] = 0), the debug interrupt does not occur immediately. Instead, instruction execution continues, and
a debug interrupt occurs if and when MSR[DE] is set to 1. This enables debug interrupts, assuming software
has not cleared the UDE debug event status from the DBSR in the meantime. Upon such a "delayed" inter-
rupt, the debug interrupt handler software can query the DBSR[IDE] field to determine that the debug inter-
rupt has occurred imprecisely.
10.4.10 Instruction Value Compare (IVC) Debug Event
The instruction value compare function provides a method of comparing an instruction against a set of mask
registers and performing selected actions when a match condition occurs. The masks are implemented
through the Instruction Match (IMR) and Instruction Match Mask (IMMR) registers. The IMR contains the
instruction compare data, and the IMMR is used to hold a 32-bit mask. A match occurs when the instruction
data bitwise ANDed against the IMMR equals the IMR also bitwise ANDed against the IMMR. An instruction
value compare debug event is enabled by setting DBCR3[IVC].
When enabled, the occurrence of an IVC debug event is recorded in DBSR[IVC]. If debug interrupts are not
enabled (MSR[DE] = 0), the imprecise debug event (DBSR[IDE]) bit is also set. The resulting actions taken by
the processor due to the IVC debug event depend on the specific debug configuration.
When operating in external debug mode (DBCR0[EDM] = 1), the setting of PCCR0[DBA] determines the
resulting debug actions. If the debug action is a stop, the processor enters the stop state and ceases the
processing of instructions. The program counter contains the address of the instruction that caused the IVC
match to occur. If the PCCR0[DBA] decode does not stop the processor, instruction execution continues, and
any additional debug actions are determined by the setting of DBCR0[IDM].
When operating in internal debug mode (DBCR0[IDM] = 1) with debug interrupts enabled (MSR[DE] = 1), a
debug interrupt occurs with CSRR0 set to the address of the instruction that caused the IVC debug event.
When operating in internal debug mode with debug interrupts disabled (MSR[DE] = 0), the debug interrupt
does not occur immediately. Instead, instruction execution continues, and a debug interrupt occurs if and
when MSR[DE] is set to 1. This enables debug interrupts, assuming software has not cleared the IVC debug
event status from the DBSR in the meantime. Upon such a "delayed" interrupt, the debug interrupt handler
software can query the DBSR[IDE] field to determine that the debug interrupt has occurred imprecisely.
Debug Facilities
Version 1.3
Page 414 of 864
October 23, 2012
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