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User's Manual
A2 Processor
Table C-13. XU Debug Mux3 Debug and Trigger Groups
Debug Group
11
0:0
1:1
2:2
3:3
4:4
5:7
8:8
9:9
10:10
11:12
13:13
14:15
16:16
17:17
18:21
22:25
26:26
27:27
28:35
36:43
44:51
52:65
66:87
12
0:0
1:3
4:5
6:6
7:7
8:12
13:20
21:21
22:29
30:36
37:43
44:51
52:52
53:57
58:64
65:65
66:72
73:80
81:81
82:82
83:83
84:84
Debug and Trigger Groups
Page 822 of 864
ldq_rel1_val
ldq_rel_mid_val
ldq_rel3_val
ldq_rel_retry_val
ldq_recirc_rel_val
ldq_rel_tag
ldq_rel_set_val
ldq_rel_ci
ldq_rel_back_invalidated
ldq_rel_ta_gpr(7:8)
ldq_rel_lock_en
ldq_rel_classid
spr_xucr0_dcdis_q
xucr0_clo_q
reld_q_val(0:3)
reld_q_val(4:7)
rel_m_q_upd
reld_q_early_byp
rel_m_q_way_q
rel2_wlock_q
rel_way_dwen
ldq_rel_addr
ldq_rel_addr
ldq_rel1_val
ldq_rel_tag
ldq_rel_classid
rel_fxubyp_val
rel_relbyp_val
rel_congr_cl_q
rel2_wlock_q
rel_val_wen_q
way_not_empty
rel_op_lru
rel_lru_val_q
rel_way_dwen
xucr0_clo_q
ex4_congr_cl_q
xu_op_lru
ex6_c_acc_val_q
ex6_lru_upd_q
ex4_way_hit_q
ex4_c_acc_q
spr_xucr0_dcdis_q
ex4_fxubyp_val
ex4_relbyp_val
(Sheet 4 of 11)
Signal List
Version 1.3
October 23, 2012
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