Dcc Operations - IBM A2 User Manual

User's Manual
A2 Processor
Extensive load, store, and flush queues are also provided, such that up to eight outstanding load misses with
the DCC continuing to service subsequent load and store hits in an in-order fashion.
The rest of this section describes each of these functions in more detail.

5.5.1 DCC Operations

When the DCC executes a load, store, or data cache management instruction, the DCC first translates the
effective address specified by the instruction into a real address (see Memory Management on page 185 for
more information about address translation). Next, the DCC accesses the data cache array for the cache line
associated with the real address of the requested data. If the cache line is found in the array (a cache hit),
that cache line is used to satisfy the request, according to the type of operation (load, store, and so on).
If the cache line is not found in the array (a cache miss), the next action depends upon the type of instruction
being executed, as well as the storage attributes of the memory page containing the data being accessed.
For most operations, and assuming the memory page is cacheable (see Caching Inhibited (I) on page 196),
the DCC sends a request for the entire cache line (64 bytes) to the system interface. The request to the
system interface is sent using the specific byte address requested by the instruction, so that the memory
subsystem can read the cache line target word first (if it supports such operation) and supply the specific
bytes requested before retrieving the rest of the cache line.
While the DCC is waiting for a cache line read to complete, it can continue to process subsequent instructions
and handle those accesses that hit in the data cache. That is, the data cache is completely nonblocking.
As the DCC receives each portion of the cache line from the data read A2 core interface, data can be
bypassed to the GPR file to satisfy load instructions, without waiting for the entire cache line to be filled. Data
is written into the data cache immediately.
Once a data cache line read request has been made, the entire line read is performed and the line is written
into the data cache. The DCC never aborts any A2 core interface request once it has been made, except
when a processor reset occurs while the request is being made.
The DCC does not initiate speculative loads. Load requests to memory are always initiated in program order.
Write requests to memory cannot be initiated speculatively.
If the guarded storage attribute is set for the memory page being accessed, then the memory request will not
be initiated until it is guaranteed that the access is required by the SEM. Once initiated, the access will not be
abandoned, and the instruction is guaranteed to complete before any change in the instruction stream. That
is, if the instruction stream is interrupted, then upon return the instruction execution resumes after the instruc-
tion that accessed guarded storage, such that the guarded storage access will not be re-executed.
See Guarded (G) on page 196 for more information about accessing guarded storage.
Programming Note:
It is a programming error for a load, store, or dcbz instruction to reference a valid cache line in the data
cache if the caching inhibited storage attribute is set for the memory page containing the cache line. The
result of such an access is undefined. After processor reset, hardware automatically sets the caching
inhibited storage attribute for the memory page containing the reset address. Software should flash inval-
idate the data cache (using dci; see Data Cache Management Instruction Summary on page 177) before
executing any load, store, or dcbz instructions. Subsequently, lines are not placed into the data cache
unless they are accessed by reference to a memory page for which the caching inhibited attribute has
been turned off. If software subsequently turns on the caching inhibited storage attribute for such a page,
Instruction and Data Caches
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October 23, 2012