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3.2 Floating-Point Exceptions
Each floating-point exception, and each category of invalid operation exception, is associated with an excep-
tion bit in the FPSCR. The following floating-point exceptions are detected by the processor. The associated
FPSCR fields are listed with each exception and invalid operation exception category.
• Invalid operation exception (VX)
Table 3-2. Invalid Operation Exception Categories
SNaN
Infinity – Infinity
Infinity Infinity
Zero Zero
Infinity Zero
Invalid Compare
Software Request
Invalid Square Root
Invalid Integer Convert
• Zero divide exception (ZX)
• Overflow exception (OX)
• Underflow exception (UX)
• Inexact exception (XI)
Each floating-point exception also has a corresponding enable bit in the FPSCR. See Floating-Point Status
and Control Register Instructions on page 151 for descriptions of these exception and enable bits and FU
Interrupts and Exceptions on page 371 for a detailed discussion of floating-point exceptions including the
effects of the FPSCR enable bits.
3.3 Floating-Point Registers
This section provides an overview of the register types implemented in the A2 core. Detailed descriptions of
the floating-point registers are provided within the chapters covering the functions with which they are associ-
ated. An alphabetical summary of all registers, including bit definitions, is provided in Register Summary on
page 529.
Certain bits in some registers are reserved and thus not necessarily implemented. For all registers with fields
marked as reserved, these reserved fields should be written as 0 and read as undefined. The recommended
coding practice is to perform the initial write to a register with reserved fields set to 0, and to perform all
subsequent writes to the register using a read-modify-write strategy. That is, read the register; use logical
instructions to alter defined fields, leaving reserved fields unmodified; and write the register.
Each register is classified as being of a particular type, as characterized by the specific instructions used to
read and write registers of that type. The registers contained within the A2 core are defined by Book III-E.
Version 1.3
October 23, 2012
Category
FPSCR Field
VXSNAN
VXISI
VXIDI
VXZDZ
VXIMZ
VXVC
VXSOFT
VXSQRT
VXCVI
User's Manual
A2 Processor
FU Programming Model
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