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User's Manual
A2 Processor
The following is a prioritized listing of the various exceptions that cause a data storage interrupt and the corre-
sponding ESR bit, if applicable. Even though multiples of these exceptions can occur, at most one of the
following exceptions is reported in the ESR:
• Cache locking: DLK0:1
• Page table fault: PT
• Virtualization fault
• TLB ineligible: TLBI
• Byte ordering: BO
• Read access or write access: If the exception occurred during a page table translation: PT
• Unavailable coprocessor type: UCT
7.6.4 Instruction Storage Interrupt
An instruction storage interrupt occurs when no higher priority exception exists and an instruction storage
exception is presented to the interrupt mechanism. Note that although an instruction storage exception can
occur during an attempt to fetch an instruction, such an exception is not actually presented to the interrupt
mechanism until an attempt is made to execute that instruction. The A2 core includes the following types of
instruction storage exceptions:
CPU Interrupts and Exceptions
Page 334 of 864
AXU Set to 1 if the instruction causing the interrupt is an auxiliary
processor load or store; otherwise, set to 0.
BO
Set to 1 if the instruction caused a byte ordering exception;
otherwise, set to 0.
Note that a read or write access control exception can occur
in combination with a byte ordering exception, in which case
software needs to examine the TLB entry associated with the
address reported in the DEAR to determine whether both
exceptions occurred, or just a byte ordering exception.
EPID Set to 1 if the instruction causing the interrupt is an external
process ID instruction; otherwise, set to 0.
TLBI Set to 1 if a TLB ineligible exception occurred during a page
table translation for the instruction causing the interrupt;
otherwise, set to 0.
PT
Set to 1 If a page table fault or read or write access control
exception occurred during a page table translation for the
instruction causing the interrupt, or if no TLB entry was
created from the page table. Set to an implementation-depen-
dent value if a TLB entry was created; otherwise, set to 0.
UCT Set to 1 if an unavailable coprocessor type exception
occurred; otherwise, set to zero.
All other defined ESR bits are set to 0.
Version 1.3
October 23, 2012
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