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User's Manual
A2 Processor
• A floating-point or AXU load or store instruction that references a data storage operand that is not aligned
on an operand-sized boundary, when XUCR0[AFLSTA].
• An icswx[.] or icswepx[.] instruction specifying a coprocessor-request block (CRB) that is not located on
a 128-byte boundary.
• A dcbz instruction that targets a memory page that is either write-through required or caching inhibited.
• A boundary is crossed between memory pages with different storage attributes. See Section 6.5 on
page 195 for a definition of the various storage attributes.
• An alignment interrupt occurs regardless of whether a stwcx. or stdcx. would have performed its store.
The CR[CR0] is not updated.
Programming Note: The architecture does not support the use of an unaligned effective address by the
lwarx, ldarx, stwcx. and stdcx. instructions. If an alignment interrupt occurs due to the attempted execution
of one of these instructions, the alignment interrupt handler must not attempt to emulate the instruction;
instead, it should treat the instruction as a programming error.
When an alignment interrupt occurs, the processor suppresses the execution of the instruction causing the
alignment exception, the interrupt processing registers are updated as indicated in the following list (all regis-
ters not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || 0x0C0.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Data Exception Address Register
(DEAR)
Exception Syndrome Register (ESR)
7.6.7 Program Interrupt
A program interrupt occurs when no higher priority exception exists, a program exception is presented to the
interrupt mechanism, and—for the floating-point enabled form of program exception only—MSR[FE0,FE1] is
nonzero. The A2 core includes following types of program exception:
CPU Interrupts and Exceptions
Page 338 of 864
Set to the effective address of the instruction causing the alignment
interrupt.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Set to the effective address of a byte that is both within the range of
the bytes being accessed by the storage access or cache manage-
ment instruction and within the page whose access caused the
alignment exception.
FP
Set to 1 if the instruction causing the interrupt is a floating-
point load or store; otherwise, set to 0.
ST
Set to 1 if the instruction causing the interrupt is a store,
dcbz, or dcbi instruction; otherwise, set to 0.
AXU Set to 1 if the instruction causing the interrupt is an auxiliary
processor load or store; otherwise, set to 0.
EPID Set to 1 if the instruction causing the interrupt is an external
process ID instruction; otherwise, set to 0.
All other defined ESR bits are set to 0.
Version 1.3
October 23, 2012
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