Machine Check Save/Restore Register 0 (Mcsrr0); Machine Check Save/Restore Register 1 (Mcsrr1) - IBM A2 User Manual

Bits Field Name
59 DS
60:63 ///

7.5.11 Machine Check Save/Restore Register 0 (MCSRR0)

MCSRR0 is an SPR that is used to save the machine state on machine check interrupts and to restore the
machine state when an rfmci is executed. When a machine check interrupt occurs, MCSRR0 is set to an
address associated with the process that was executing at the time. When rfmci is executed, instruction
execution returns to the address in MCSRR0.
In general, MCSRR0 contains the address of the instruction that caused the machine check interrupt or the
address of the instruction to return to after a machine check interrupt is serviced. See the individual descrip-
tions under Interrupt Definitions on page 323 for an explanation of the precise address recorded in MCSRR0
for each machine check interrupt type.
MCSRR0 can be written from a GPR using mtspr and can be read into a GPR using mfspr.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
0:61 SRR0
62:63 ///

7.5.12 Machine Check Save/Restore Register 1 (MCSRR1)

MCSRR1 is an SPR that is used to save the machine state on machine check interrupts and to restore the
machine state when an rfmci is executed. When a machine check interrupt is taken, the contents of the MSR
(before the MSR is cleared by the interrupt) are placed into MCSRR1. When rfmci is executed, the MSR is
restored with the contents of MCSRR1.
Bits of MCSRR1 that correspond to reserved bits in the MSR are also reserved.
Programming Note: An MSR bit that is reserved can be altered by rfmci, consistent with the value being
restored from MCSRR1.
Version 1.3
October 23, 2012
Initial
Value
0b0 Data Address Space
0 The processor directs all data storage accesses to address space 0 (TS = 0 in the
relevant TLB entry).
1 The processor directs all data storage accesses to address space 1 (TS = 1 in the
relevant TLB entry).
0b0000 Reserved
MCSRR0
570
0x0000000000000000
N
Initial
Value
0x0 Critical Save/Restore Register 0
Machine Check Save/Restore Register 0 (MCSRR0) is used to save the machine state on
machine check interrupts and to restore the machine state when an rfmci is executed.
When a machine check interrupt is taken, the MCSRR0 is set to the current or next instruc-
tion address. When rfmci is executed, instruction execution continues at the address in
MCSRR0. In general, MCSRR0 contains the address of an instruction that was executing
or about to be executed when the machine check exception occurred.
0b00 Reserved
Description
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
AM
func
CPU Interrupts and Exceptions
Page 313 of 864