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The following table illustrates the fields of the XER, while Table 2-38 and Table 2-39 list the instructions that
update XER[SO,OV] and the XER[CA] fields, respectively. The sections that follow the figure and tables
describe the fields of the XER in more detail.
Access to the XER is nonprivileged.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
0:31
///
32
SO
33
OV
34
CA
35:56
///
57:63
SI
Table 2-38. XER[SO,OV] Updating Instructions
Add
addo
.
subfo
[
]
addco
.
subfco
[
]
addeo
.
subfeo
[
]
addmeo
.
subfmeo
[
]
addzeo
.
subfzeo
[
]
Table 2-39. XER[CA] Updating Instructions
Integer Arithmetic
Add
addc
o
.
[
][
]
adde
o
.
[
][
]
addic
.
[
]
addme
o
.
[
][
]
addze
o
.
[
][
]
Version 1.3
October 23, 2012
XER
1
0x0000000000000000
N
Initial
Value
0x0
Reserved
0b0
Summary Overflow
The Summary Overflow bit is set to 1 whenever an instruction (except mtspr) sets the
Overflow bit.
0b0
Overflow
The Overflow bit is set to indicate that an overflow has occurred during execution of an
instruction.
0b0
Carry
Carry bit from extend arithmetic operations.
0x0
Reserved
0x0
String Index
This field specifies the number of bytes to be transferred by a Load String Indexed or Store
String Indexed instruction.
Integer Arithmetic
Subtract
Multiply
.
[
]
.
mullwo
.
[
]
[
]
.
[
]
.
mulldo[.]
[
]
.
[
]
Subtract
subfc
o
.
[
][
]
subfe
o
.
[
][
]
subfic
subfme
o
.
[
][
]
subfze
o
.
[
][
]
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Divide
Negate
divwo
.
[
]
divwuo
.
[
]
nego
.
[
]
divdo[.]
divduo[.]
Integer Shift
Shift Right Algebraic
sraw
.
[
]
srawi
.
[
]
srad
.
[
]
sradi
.
[
]
User's Manual
A2 Processor
Any
Any
Y
func
Processor Control
Register Management
mtspr
mcrxr
Processor Control
Register Management
mtspr
mcrxr
CPU Programming Model
Page 111 of 864
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