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1. DBSR, MCSR, and TSR have read/clear access. These three registers are status registers, and as such
behave differently than other SPRs when written. The term "read/clear" does not mean that these regis-
ters are automatically cleared upon being read. Rather, the "clear" refers to their behavior when being
written. Instead of simply overwriting the SPR with the data in the source GPR, the status SPR is updated
by zeroing those bit positions corresponding to 1 values in the source GPR; those bit positions corre-
sponding to 0 values in the source GPR are left unchanged. In this fashion, it is possible for software to
read one of these status SPRs, and then write to it using the same data that was read. Any bits that were
read as 1 are then cleared, and any bits that were not yet set at the time the SPR was read are left
unchanged. If any of these previously clear bits happen to be set between the time the SPR is read and
when it is written, then when the SPR is later read again, software observes any newly set bits. If it were
not for this behavior, software could erroneously clear bits that it had not yet observed as having been set,
and overlook the occurrence of certain exceptions.
14.2 Reserved Fields
For all registers with fields marked as reserved, the reserved fields should be written as zero and read as
undefined. That is, when writing to a reserved field, write a zero to that field. When reading from a reserved
field, ignore that field.
The recommended coding practice is to perform the initial write to a register with reserved fields as described
in the preceding paragraph, and to perform all subsequent writes to the register using a read-modify-write
strategy: read the register, alter desired fields with logical instructions, and then write the register.
Note: Software must not set any field of a system register to a reserved value.
14.3 Unimplemented SPRs
An unimplemented SPR is defined as any SPR number that is not listed in Table 14-1.
14.4 Device Control Registers
Move to and move from DCR instructions when CCR2(EN_DCR) is zero are dropped silently; they are no-ops
and do not cause an exception.
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Register Summary
Page 535 of 864
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