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Bits
Field Name
62
LOCK
63
VALID
10.9.7 Execution Unit Debug Register 2 (XUDBG2)
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
32
///
33:63
TAG
10.10 Thread Control and Status
The SCOM-accessible Thread Control and Status Register (THRCTL) allows debug control of thread opera-
tions such as start/stop, single-step and the monitoring of thread status bits. It is connected to the boot config-
uration ring and is configurable through scanning during the POR sequence. This section contains a brief
description of these debug functions, the THRCTL register bit definition, and a few sample procedures.
The Tx_STOP controls cause instruction fetching to stop and the thread to enter a stopped state. When
stopped, the following events occur:
• The IU stops fetching instructions; the next instruction address is preserved and used upon restart.
• Commands in the pipeline continue to completion. If a stop is attempted in the middle of a uCode
sequence, the hardware allows the uCode sequence to complete before stopping.
• The Tx_RUN status is reset to indicate that the thread is stopped.
• Snoop invalidate and TLB invalidate requests from the L2 are still handled as normal.
To single-step instructions, first put the core in debug mode (PC Configuration Register 0, bit 32 = 1) with the
designated thread stopped using the Tx_STOP control. Each time the Tx_STEP control is set to '1', the IU
issues one instruction.
Version 1.3
October 23, 2012
Initial
Value
0b0
Data Cache Directory Lock Bits
0
Directory entry is unlocked.
1
Directory entry is locked.
0b0
Data Cache Directory Read Valid
0
Directory entry is not valid.
1
Directory entry is valid.
XUDBG2
887
0x0000000000000000
Y
Initial
Value
0b0
Reserved
0x0
Data Cache Directory Tag
Indicates value of the tag bit in the data cache directory.
Description
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
None
N
func
Debug Facilities
Page 441 of 864
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