Data Byte Ordering - IBM A2 User Manual

User's Manual
A2 Processor
Consider the big-endian mapping of instruction p at address 0x00, where, for example, p = add r7, r7, r4:
MSB
0x00 0x01 0x02
On the other hand, in a little-endian mapping the same instruction is arranged with the least-significant byte
(LSB) of the instruction word at the lowest-numbered address:
LSB
0x00 0x01 0x02
By the definition of Power ISA bit numbering, the most-significant byte of an instruction is the byte containing
bits 0:7 of the instruction. As depicted in the instruction format diagrams (see Instruction Formats in the
Power ISA specification), this most-significant byte is the one that contains the primary opcode field (bits 0:5).
Due to this difference in byte orderings, the processor must perform whatever byte reversal is required
(depending on the particular byte ordering in use) to correctly deliver the opcode field to the instruction
decoder. In the A2 core, this reversal is performed between the memory interface and the instruction cache,
according to the value of the endian storage attribute for each memory page, such that the bytes in the
instruction cache are always correctly arranged for delivery directly to the instruction decoder.
If the endian storage attribute for a memory page is reprogrammed from one byte ordering to the other, the
contents of the memory page must be reloaded with program and data structures that are in the appropriate
byte ordering. Furthermore, anytime the contents of instruction memory change, the instruction cache must
be made coherent with the updates by invalidating the instruction cache and refetching the updated memory
contents with the new byte ordering.

2.2.3.3 Data Byte Ordering

Unlike instruction fetches, data accesses cannot be byte-reversed between memory and the data cache.
Data byte ordering in memory depends upon the data type (byte, halfword, word, and so on) of a specific data
item. It is only when moving a data item of a specific type from or to an architected register (as directed by the
execution of a particular storage access instruction) that it becomes known what kind of byte reversal might
be required due to the byte ordering of the memory page containing the data item. Therefore, byte reversal
during load or store accesses is performed between the data cache (or memory, on a data cache miss, for
example) and the load register target or store register source, depending on the specific type of load or store
instruction (that is, byte, halfword, word, and so on).
Comparing the big-endian and little-endian mappings of structure
ples on page 66, the differences between the byte locations of any data item in the structure depends upon
the size of the particular data item. For example (again referring to the big-endian and little-endian mappings
s
of structure ):
• The word a has its 4 bytes reversed within the word spanning addresses 0x00 – 0x03.
• The halfword e has its 2 bytes reversed within the halfword spanning addresses 0x1C – 0x1D.
Note: The array of bytes d, where each data item is a byte, is not reversed when the big-endian and little-
endian mappings are compared. For example, the character 'A' is located at address 0x14 in both the big-
endian and little-endian mappings.
The size of the data item being loaded or stored must be known before the processor can decide whether,
and if so, how, to reorder the bytes when moving them between a register and the data cache (or memory).
CPU Programming Model
Page 68 of 864
LSB
0x03
MSB
0x03
s
, as shown in Structure Mapping Exam-
Version 1.3
October 23, 2012