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Table C-7. MMU Debug Multiplexer Debug and Trigger Groups
Debug Group
12
dbg_group12a(60 to 63) <= tlb_ctl_dbg_clr_resv_q(0 to 3); -- tag5
(continued)
dbg_group12a(64 to 67) <= tlb_ctl_dbg_clr_resv_terms(0 to 3); -- tag5, threadwise condensed into to tlbivax,
dbg_group12a(68 to 71) <= htw_dbg_req_valid_q(0 to 3);
dbg_group12a(72 to 75) <= htw_dbg_resv_valid_vec(0 to 3);
dbg_group12a(76 to 79) <= htw_dbg_tag4_clr_resv_q(0 to 3);
dbg_group12a(80 to 83) <= htw_dbg_tag4_clr_resv_terms(0 to 3); -- tag4, threadwise condensed into to tlbivax,
dbg_group12a(84 to 87) <= "0000";
-- tlb_low_data
-- [0:51]
-- [52:55]
-- [56:59]
-- [60:61]
-- [62]
-- [63]
-- [64:65]
-- [66:73]
-- [74:83]
dbg_group12b(0 to 83)
dbg_group12b(84)
dbg_group12b(85)
dbg_group12b(86)
dbg_group12b(87)
dbg_group12
Version 1.3
October 23, 2012
tlbilx, tlbwe, ptereload
tlbilx, tlbwe, ptereload
EPN
SIZE (4b)
ThdID
Class
ExtClass
TID_NZ
Reserved (2b)
8b for LPID
Parity 10bits
<= tlb_cmp_dbg_tag5_way(0 to 83); -- tag5 way epn
<= (tlb_cmp_dbg_tag5_lru_dataout(0) and tlb_cmp_dbg_tag5_wayhit(0)) or
(tlb_cmp_dbg_tag5_lru_dataout(1) and tlb_cmp_dbg_tag5_wayhit(1)) or
(tlb_cmp_dbg_tag5_lru_dataout(2) and tlb_cmp_dbg_tag5_wayhit(2)) or
(tlb_cmp_dbg_tag5_lru_dataout(3) and tlb_cmp_dbg_tag5_wayhit(3)); -- valid
<= (tlb_cmp_dbg_tag5_lru_dataout(8) and tlb_cmp_dbg_tag5_wayhit(0)) or
(tlb_cmp_dbg_tag5_lru_dataout(9) and tlb_cmp_dbg_tag5_wayhit(1)) or
(tlb_cmp_dbg_tag5_lru_dataout(10) and tlb_cmp_dbg_tag5_wayhit(2)) or
(tlb_cmp_dbg_tag5_lru_dataout(11) and tlb_cmp_dbg_tag5_wayhit(3)); -- iprot
<= tlb_cmp_dbg_tag5_lru_dataout(4);
<= (not(tlb_cmp_dbg_tag5_lru_dataout(4)) and tlb_cmp_dbg_tag5_lru_dataout(5)) or
(tlb_cmp_dbg_tag5_lru_dataout(4) and tlb_cmp_dbg_tag5_lru_dataout(6)); -- encoded
lru way lsb
<= dbg_group12b when mmucr2(9)='1' else dbg_group12a;
(Sheet 11 of 16)
Signal List
User's Manual
A2 Processor
-- encoded lru way msb
Debug and Trigger Groups
Page 791 of 864
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