Data Storage Interrupt - IBM A2 User Manual

User's Manual
A2 Processor
Bits Field Name
59 TLBMH
60 IEPE
61 DEPE
62 TLBPE
63 ///
See Machine Check Interrupts on page 296 for more information about the handling of machine check inter-
rupts within the A2 core.

7.6.3 Data Storage Interrupt

A data storage interrupt might occur when no higher priority exception exists and a data storage exception is
presented to the interrupt mechanism. The A2 core includes the following types of data storage exceptions:
Cache Locking Exception
If a cache locking instruction is executed in user mode (MSR[PR] = 1), a data storage interrupt occurs if any
of the following conditions are met:
• (MSRP[UCLEP] = 1 & MSR[GS] = 1).
• (MSRP[UCLEP] = 0 | MSR[GS] = 0) and MSR[UCLE] = 0.
When a cache locking type data storage interrupt occurs, one of the following ESR or GESR bits is set to 1:
Bit
42 DLK
0
0 Default setting.
1 A dcbtls, dcbtstls, or dcblc instruction was executed in user mode.
43 DLK
1
0 Default setting.
1 An icbtls or icblc instruction was executed in user mode.
Read Access Control Exception
A read access control exception is caused by one of the following cases:
• While in user mode (MSR[PR] = 1), a load instruction attempts to access a location in storage that is not
enabled for read access in user mode (that is, the TLB entry associated with the memory page being
accessed has UR = 0).
• While in supervisor mode (MSR[PR] = 0), a load instruction attempts to access a location in storage that
is not enabled for read access in supervisor mode (that is, the TLB entry associated with the memory
page being accessed has SR = 0).
See Access Control Applied to Cache Management Instructions on page 194.
CPU Interrupts and Exceptions
Page 330 of 864
Initial
Value
0b0 TLB Multi-Hit Error
1 Indicates a multiple entry hit error detected for a TLB compare.
0b0 I-ERAT Parity Error
1 Indicates a parity error detected for an I-ERAT eratre, eratsx, or compare.
0b0 D-ERAT Parity Error
1 Indicates a parity error detected for a D-ERAT eratre, eratsx, or compare.
0b0 TLB Parity Error
1 Indicates a parity error detected for a TLB tlbre, tlbsx, or reload.
0b0 Reserved
Description
Description
Version 1.3
October 23, 2012