IBM A2 User Manual page 417

Bits Field Name
41 IAC2
42 IAC3
43 IAC4
44:45 DAC1
46:47 DAC2
48 RET
49:58 ///
59:60 DAC3
61:62 DAC4
63 FT
Version 1.3
October 23, 2012
Initial
Value
0b0 Instruction Address Compare 2 Debug Event Enable
0 IAC2 debug events cannot occur.
1 IAC2 debug events can occur.
0b0 Instruction Address Compare 3 Debug Event Enable
0 IAC3 debug events cannot occur.
1 IAC3 debug events can occur.
0b0 Instruction Address Compare 4 Debug Event Enable
0 IAC4 debug events cannot occur.
1 IAC4 debug events can occur.
0b00 Data Address Compare 1 Debug Event Enable
00 Disabled: DAC1 debug events cannot occur.
01 Store only: DAC1 debug events can occur only if a store-type data storage
access.
10 Load only: DAC1 debug events can occur only if a load-type data storage access.
11 Any: DAC1 debug events can occur on any data storage access.
0b00 Data Address Compare 2 Debug Event Enable
00 Disabled: DAC2 debug events cannot occur.
01 Store only: DAC2 debug events can occur only if a store-type data storage
access.
10 Load only: DAC2 debug events can occur only if a load-type data storage access.
11 Any: DAC2 debug events can occur on any data storage access.
0b0 Return Debug Event Enable
0 RET debug events cannot occur.
1 RET debug events can occur.
0x0 Reserved
0b00 Data Address Compare 3 Debug Event Enable
00 Disabled: DAC3 debug events cannot occur.
01 Store only: DAC3 debug events can occur only if a store-type data storage
access.
10 Load only: DAC3 debug events can occur only if a load-type data storage access.
11 Any: DAC3 debug events can occur on any data storage access.
0b00 Data Address Compare 4 Debug Event Enable
00 Disabled: DAC4 debug events cannot occur.
01 Store only: DAC4 debug events can occur only if a store-type data storage
access.
10 Load only: DAC4 debug events can occur only if a load-type data storage access.
11 Any: DAC4 debug events can occur on any data storage access.
0b0 Freeze Timers on Debug Event
0 Enable clocking of timers.
1 Disable clocking of timers if any DBSR bit is set (except MRR).
Description
User's Manual
A2 Processor
Debug Facilities
Page 417 of 864