User Decrementer (Udec) - IBM A2 User Manual

Using mtspr to force the DEC to 0 does not cause a decrementer exception, and thus does not cause
TSR[DIS] to be set. However, if a time base clock causes a decrement from a DEC value of 1 to occur simul-
taneously with the writing of the DEC by an mtspr instruction, then the decrementer exception does occur,
TSR[DIS] is set, and the DEC is written with the value from the mtspr.
For software to quiesce the activity of the DEC and eliminate all DEC exceptions, follow this procedure:
1. Write 0 to TCR[DIE]. This prevents a decrementer exception from causing a decrementer interrupt.
2. Write 0 to TCR[ARE]. This disables the DEC auto-reload feature.
3. Write 0 to the DEC to halt decrementing. Although this action does not itself cause a decrementer excep-
tion, it is possible that a decrement from a DEC value of 1 has occurred since the last time that TSR[DIS]
was cleared.
4. Write 1 to TSR[DIS] (DEC Interrupt Status bit). This clears the decrementer exception by setting
TSR[DIS] to 0. Because the DEC is no longer decrementing (due to having been written with 0 in step 3),
no further decrementer exceptions are possible.

9.3 User Decrementer (UDEC)

The UDEC is a 32-bit SPR that decrements at the same rate that the time base increments. The UDEC is
read and written using mfspr and mtspr, respectively. When a nonzero value is written to the UDEC, it
begins to decrement with the next time base clock. A user decrementer exception is signalled when:
• A decrement occurs on a UDEC count of 1, and
• The User Decrementer Interrupt Status field of the Timer Status Register (TSR[UDIS] (see page 397) is
set, and
• The exception is enabled by either the External Interrupt Enable or Guest State fields of the Machine
State Register (MSR[EE] or MSR[GS] (see Section 7.5.2 Machine State Register (MSR) on page 301).
Section 7 CPU Interrupts and Exceptions on page 293 provides more information about the handling of User
Decrementer interrupts.
The user decrementer interrupt handler software should clear TSR[UDIS] before re-enabling MSR[EE] or
MSR[GS] to avoid another user decrementer interrupt due to the same exception (unless TCR[UDIE] is
cleared instead).
When the UDEC decrements from a value of 1, the UDEC simply decrements to the value 0, and then stops
decrementing until it is re-initialized by software.
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Version 1.3
October 23, 2012
UDEC
550
0x000000007FFFFFFF
N
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
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