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User's Manual
A2 Processor
executed next (that is, the instruction after the one that updated MSR[FE0,FE1]). If the MSR was updated by
an rfi, rfci, rfgi, or rfmci instruction, SRR0 is set to the address to which the rfi, rfci, or rfmci was returning,
and not to the instruction address that is sequentially after the rfi, rfci, rfgi, or rfmci.
The second type of delayed interrupt that can be handled as a synchronous, imprecise interrupt is the debug
interrupt. Similar to the floating-point enabled exception type of program interrupt, the debug interrupt can be
temporarily disabled by an MSR bit, MSR[DE]. Accordingly, certain kinds of debug exceptions can occur and
be recorded in the Debug Status Register (DBSR) while MSR[DE] is 0, and later lead to a delayed debug
interrupt if MSR[DE] is set to 1 while a debug exception is still set in the DBSR. If and when this occurs, the
interrupt is either synchronous and imprecise or it is asynchronous, depending on the type of debug excep-
tion causing the interrupt. In either case, CSRR0 is set to the address of the instruction that would have
executed next (that is, the instruction after the one that set MSR[DE] to 1). If MSR[DE] is set to 1 by rfi, rfci,
rfgi, or rfmci, CSRR0 is set to the address to which the rfi, rfci, rfgi, or rfmci was returning, and not to the
address of the instruction that was sequentially after the rfi, rfci, rfgi, or rfmci.
Another interrupt that is handled as a synchronous, imprecise interrupt is the debug interrupt, when using the
data value compare (DVC) facility on a load instruction.
Besides these special cases of program and debug interrupts, all other synchronous interrupts are handled
precisely by the A2 core, except the FP enabled exception type of program interrupts when the processor is
operating in one of the architecturally-defined imprecise modes (MSR[FE0,FE1] != 0b00).
See Program Interrupt on page 338 and Debug Interrupt on page 347 for a more detailed description of these
interrupt types, including both the precise and imprecise cases.
7.3.3 Critical and Noncritical Interrupts
Interrupts can also be classified as critical or noncritical interrupts. Certain interrupt types demand immediate
attention, even if other interrupt types are currently being processed and have not yet had the opportunity to
save the state of the machine (that is, the return address and captured state of the MSR). To enable taking a
critical interrupt immediately after a noncritical interrupt has occurred (that is, before the state of the machine
has been saved), two sets of Save/Restore Register pairs are provided. Critical interrupts use the
Save/Restore Register pair CSRR0/CSRR1. Noncritical interrupts use Save/Restore Register pair
SRR0/SRR1 or, for interrupts directed to guest state, GSRR0/GSRR1.
7.3.4 Machine Check Interrupts
Machine check interrupts are a special case. They are typically caused by some kind of hardware or storage
subsystem failure or by an attempt to access an invalid address. A machine check can be caused indirectly
by the execution of an instruction, but not be recognized or reported until long after the processor has
executed past the instruction that caused the machine check. As such, machine check interrupts cannot
properly be classified as either synchronous or asynchronous, nor as precise or imprecise. They also do not
belong to either the critical or the noncritical interrupt class. Instead, machine check interrupts have associ-
ated with them a unique pair of save/restore registers, Machine Check Save/Restore Registers 0/1
(MCSRR0/1).
Architecturally, the following general rules apply for Machine Check interrupts:
1. No instruction after the one whose address is reported to the machine check interrupt handler in
MCSRR0 has begun execution.
2. The instruction whose address is reported to the machine check interrupt handler in MCSRR0, and all
prior instructions, might or might not have completed successfully. All those instructions that are ever
CPU Interrupts and Exceptions
Page 296 of 864
Version 1.3
October 23, 2012
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