IBM A2 User Manual page 123

Under certain circumstances, it is necessary for the hardware or software to force the synchronization of a
program's context. Context synchronizing operations include all interrupts except machine check, as well as
the isync, sc, rfi, rfci, and rfmci instructions. Context synchronizing operations satisfy the following require-
ments:
1. The operation is not initiated until all instructions preceding the operation have completed to the point at
which they have reported any and all exceptions that they will cause.
2. All instructions preceding the operation must complete in the context in which they were initiated. That is,
they must not be affected by any context changes caused by the context synchronizing operation or by
any instructions after the context synchronizing operation.
3. If the operation is the sc instruction (which causes a system call interrupt) or is itself an interrupt, the
operation is not initiated until no higher priority interrupt is pending (see CPU Interrupts and Exceptions
on page 293).
4. All instructions that follow the operation must be refetched and executed in the context that is established
by the completion of the context synchronizing operation and all of the instructions that preceded it.
Note that context synchronizing operations do not force the completion of storage accesses, nor do they
enforce any ordering amongst accesses before and/or after the context synchronizing operation. If such
behavior is required, then a storage synchronizing instruction must be used (see Storage Ordering and
Synchronization on page 124).
Also note that, architecturally, machine check interrupts are not context synchronizing. Therefore, an instruc-
tion that precedes a context synchronizing operation can cause a machine check interrupt after the context
synchronizing operation occurs and additional instructions have completed. For the A2 core, this can only
occur with data machine check exceptions, and not instruction machine check exceptions.
The following scenarios use pseudocode examples to illustrate the effects of context synchronization. Subse-
quent text explains how software can further guarantee "storage ordering."
1. Consider the following self-modifying code instruction sequence:
stw XYZ Store to caching inhibited address XYZ.
isync
XYZ Fetch and execute the instruction at address XYZ.
In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after the
store has occurred to memory. There is no guarantee which XYZ instruction will execute; either the old
version or the new (stored) version might.
2. Now consider the required self-modifying code sequence:
stw Write new instruction to data cache.
dcbst Push the new instruction from the data cache to memory.
msync Guarantee that dcbst completes before subsequent instructions begin.
icbi Invalidate old copy of instruction in instruction cache.
msync Guarantee that icbi completes before subsequent instructions begin.
isync Force context synchronization, discarded instructions and refetch; fetch of
stored instruction guaranteed to get new value.
3. This example illustrates the use of isync with context changes to the debug facilities
mtdbcr0 Enable the instruction address compare (IAC) debug event.
isync Wait for the new Debug Control Register 0 (DBCR0) context to be established.
XYZ This instruction is at the IAC address; an isync is necessary to guarantee that the
Version 1.3
October 23, 2012
User's Manual
A2 Processor
CPU Programming Model
Page 123 of 864