IBM A2 User Manual page 505

for each processor in the logical partition
for each ERAT entry
n  64-log
(entry page size in bytes)
2
if {(IS = "11") AND
(entry[EPN
w:63-p
(entry[X] = 0 OR EPN
(entry[TGS] = gs) AND
(entry[TS] = ts) AND
(entry[TID] = tid
(entry[THDID] = tid
(entry[CLASS] = tid
(entry[TID_NZ] = or_reduce(tid
(entry[SIZE]) = convert_to_3bit(size)) AND
(entry[EXTCLASS] = 0)} OR
{(IS = "10") AND
(entry[CLASS] = class AND MMUCR1[I/DCTID]
(entry[EXTCLASS] = 0)} OR
{(IS = "01") AND
(entry[TID] = tid
(entry[THDID] = tid
(entry[CLASS] = tid
(entry[TID_NZ] = or_reduce(tid
(entry[EXTCLASS] = 0)} OR
{(IS = "00") AND
(entry[EXTCLASS] = 0)}
then entry[V]
An effective address EA is formed by adding an index to a base address. The index is the contents of register
RB. The base address is 0 if the RA field is 0, and is the contents of register RA
This implementation requires a valid direct page size to be specified by RS
RS is not supported by this implementation for direct pages, an illegal instruction exception is generated.
60:63
When IS = '11', all ERAT entries on all processors in the same logical partition that have all of the following
properties are made invalid. The RS and MMUCR0 registers listed are those in the processor executing the
erativax instruction.The MMUCR1 register listed is that in the processor receiving the erativax snoop.
• The EPN value of the ERAT entry is equal to EPN
w:63-p
• The X value of the ERAT entry is 0, or EPN
equals 64 - log (entry page size in bytes).
2
• The TGS value of the ERAT entry is equal to MMUCR0
• The TS value of the ERAT entry is equal to MMUCR0
• The 8-bit TID value of the ERAT entry is equal to MMUCR0
• Either the appropriate MMUCR1[I/DTTID] bit (for target I-ERAT or D-ERAT) is 0, or the 4-bit ThdID value
of the ERAT entry is equal to MMUCR0
• Either the appropriate MMUCR1[I/DCTID] bit (for target I-ERAT or D-ERAT) is 0, or the 2-bit Class value
of the ERAT entry is equal to MMUCR0
• The TID_NZ value of the ERAT entry is equal to or_reduce(MMUCR0
Version 1.3
October 23, 2012
] = EPN ) AND
w:63-p
> entry[EPN
n:51
) AND
6:13
OR MMUCR1[I/DTTID] = 0) AND
2:5
OR MMUCR1[I/DCTID] = 0) AND
0:1
0:13
) AND
6:13
OR MMUCR1[I/DTTID]
2:5
OR MMUCR1[I/DCTID]
0:1
0:13

0
n:51
TID[52:55]
TID[50:51]
]) AND
n:51
)) AND
= 0) AND
TARGET
= 0) AND
TARGET
= 0) AND
TARGET
)) AND
.
w:63-p
is greater than the value of the entry EPN
.
TGS
.
TS
.
TID[56:63]
.
.
TID[50:63]
User's Manual
A2 Processor
otherwise.
0:63
. If the page size specified by
60:63
, where n
n:51
).
Implementation Dependent Instructions
Page 505 of 864