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2.3.4.2 Instruction Unit Configuration Register 1 (IUCR1)
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits
Field Name
32:49
///
50:51
HIPRI
52:57
///
58:63
THRES
2.3.5 Resources Shared between Threads
All architected states are duplicated for each thread except for logical partitioning and memory. This allows
each thread to look independent from a software standpoint. Some nonarchitected resources are shared
between threads to save on the overall area for the core. Section 2.3.6 provides more information about
shared resources. Section 2.3.7 on page 78 provides more information about duplicated resources.
2.3.6 Shared Resources
Instruction ERAT array
L1 instruction cache array
Data ERAT array
L1 data cache array
Load miss queue
Store queue
Microcode ROM array
Branch history table
SPR registers
Instruction fetch pipeline
Instruction issue
Integer execution pipeline
Version 1.3
October 23, 2012
IUCR1
883
0x0000000000001000
Y
Initial
Value
0x0
Reserved
0b01
High Priority Privilege Level
The A2 core has three priority values implemented in hardware. This field configures which
value in PPR32[PRI] corresponds to the implementations highest priority.
00
Medium normal.
01
Medium high.
10
High.
11
Very high.
0x0
Reserved
0x0
Low Priority Minimum Issue Count
Sets the number of cycles between low priority issues, which is set by PPR32[PRI]. The
number of cycles is equal to THRES 4. This field is not used when a thread is set to high
or medium priority.
Entries can be used as shared or thread specific.
Entries can be used as shared or thread specific.
This is a configurable resource and can be set up to be shared or duplicated.
Not all SPRs are shared. See Table 14-1 Register Summary on page 530 for
more information.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
User's Manual
A2 Processor
Hypv
Hypv
Y
ccfg
CPU Programming Model
Page 77 of 864
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