Updating Cr Fields; Generation Of Qnan Results; Table 8-7. Bit Encodings For A Cr Field - IBM A2 User Manual

User's Manual
A2 Processor
Bits Field Name
32:35 CR0
36:39 CR1
40:43 CR2
44:47 CR3
48:51 CR4
52:55 CR5
56:59 CR6
60:63 CR7

8.10.2 Updating CR Fields

The floating-point compare instructions fcmpo and fcmpu specify a CR field that is updated with the
compare results.
Table 8-7 illustrates the bit encodings for a CR field containing the results of an fcmpo and fcmpu instruc-
tion.

Table 8-7. Bit Encodings for a CR Field

CR Field (Bit)
Floating-Point Less Than (FL)
0
Floating-point compare: (FRA) < (FRB)
1 Floating-Point Greater Than (FG)
Floating-point compare: (FRA) > (FRB)
2 Floating-Point Equal (FE)
Floating-point compare: (FRA) = (FRB)
3 Floating-Point Unordered (FU)
Floating-point compare: One or both of (FRA) or (FRB) is a NaN.
The mcrfs instruction moves a specified FPSCR field into a CR field.

8.10.3 Generation of QNaN Results

If a disabled invalid operation exception is caused by operating on a NaN, the value returned follows the rules
indicated in Table 8-4 on page 381.
If the exception was not caused by operating on a NaN, a QNaN must be generated. The generated QNaN
has a sign bit of 0, an exponent of all 1s, a high-order fraction bit of 1 with all other fraction bits of 0:
0x7FF8000000000000.
FU Interrupts and Exceptions
Page 386 of 864
Initial
Value
0b0000 Condition Register Field 0
0b0000 Condition Register Field 1
0b0000 Condition Register Field 2
0b0000 Condition Register Field 3
0b0000 Condition Register Field 4
0b0000 Condition Register Field 5
0b0000 Condition Register Field 6
0b0000 Condition Register Field 7
Description
Description
Version 1.3
October 23, 2012