Alignment Interrupt - IBM A2 User Manual

External Input interrupts are enabled if:
(EPCR[EXTGS] = 0) & ((MSR[GS] = 1) | (MSR[EE] = 1))
or
(EPCR[EXTGS] = 1) & (MSR[GS] = 1) & (MSR[EE] = 1)
Note: MSR[EE] also enables other interrupts. See Table 7-3 Interrupt and Exception Types on page 323.
When an external input interrupt occurs, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP]
|| 0x0A0.
If the interrupt is directed to the guest state (EPCR[EXTGS] = 1 and MSR[GS] = 1), GSRR0 and GSRR1 are
set in place of SRR0, and SRR1 respectively, and instruction execution resumes at address GIVPR[IVP] ||
0x0A0.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Programming Note: Software is responsible for taking any actions that are required by the implementation
to clear any External Input exception status (such that the External Input interrupt request input signal is
deasserted) before reenabling MSR[EE], to avoid another, redundant External Input interrupt

7.6.6 Alignment Interrupt

An alignment interrupt occurs when no higher priority exception exists and an alignment exception is
presented to the interrupt mechanism. An alignment exception occurs if execution of any of the following
instructions is attempted:
• An integer load or store instruction that references a data storage operand that is not aligned on an oper-
and-sized boundary, when XUCR0[FLSTA] is 1.
• A load or store multiple instruction that is not word aligned (load and store multiple instructions are con-
sidered to reference word operands, and hence word-alignment is required). Load and store string
instructions are considered to reference byte operands, and hence they cannot cause an alignment
exception due to XUCR0[FLSTA] being 1, regardless of the target address alignment. See Table 2-11
Operand Handling Dependent on Alignment on page 90 for more information about operand alignments.
Version 1.3
October 23, 2012
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[GICM] if the interrupt is directed to guest state;
otherwise, it is set to EPCR[ICM].
GS is left unchanged if the interrupt is directed to guest state; other-
wise, it is set to zero.
UCLE is left unchanged if the interrupt is directed to the guest state
and MSRP[UCLEP] = 1; otherwise, it is set to 0.
CE, ME, DE Unchanged.
If the interrupt is directed to guest state, bits in the MSR corre-
sponding to set bits in the MSRP register are left unchanged.
All other MSR bits set to 0.
User's Manual
A2 Processor
.
CPU Interrupts and Exceptions
Page 337 of 864