Initialization; Core Reset - IBM A2 User Manual

4. Initialization

Reset of the A2 core is performed by a flush 0 scan of all rings followed by scan initialization of specific rings
as required. Reset controls external to the core drive scan ring selection and control signals into the core
during initialization. Core reset is performed as part of the chip initialization operations during the power-on
reset sequence. Additionally, software running on individual threads can initiate reset requests, either through
debug logic or due to activation of the watchdog timer. These software-initiated reset requests are forwarded
to reset control circuitry external to the core. The resulting reset operation, if any, will scan initialize the whole
core.
This chapter describes a basic core reset sequence and the initial state of the A2 core after a reset. It also
describes how software initiates reset requests and contains a description of the initialization software
required to complete initialization so that the A2 core can begin executing application code. Initialization of
other on-chip and/or off-chip system components might also be needed in addition to the processor core
initialization described in this chapter.

4.1 Core Reset

Reset of the A2 core is controlled through an external reset controller. All scannable latches are initialized
through flush 0 and/or scan operations to the scan rings. The arrays are initialized using the ABIST engines.
A more complete reset sequence will also run LBIST and full ABIST to further verify core hardware. The reset
procedure initializes the core to a cycle-reproducible state. After reset operations complete, program execu-
tion on each thread can be initiated through activation of core control signals. The following procedure
describes the typical steps a reset controller performs during a core reset.
1. Start with grid clocks active and all core clocks held off.
2. Scan latches on all core scan rings to their flush 0 initialization values. The flush 0 scan initializes the
scannable latches to their initial value as specified in the VHDL. All nonscan latches are then clocked for
eight cycles to initialize them based on the scanned latches.
3. Scan the gptr, time, and repair rings with alternate initialization values as needed.
4. Arrays are initialized through their ABIST engines.
5. Scan the func, bcfg, dcfg, regf and abst rings to their flush 0 initialization values. The flush 0 scan initial-
izes the scannable latches on these rings to their initial value as specified in the VHDL. All nonscan
latches are then clocked for eight cycles to initialize them based on the scanned latches. The default core
initialization is for thread 0 to begin first instruction fetch when clocks start, unless held in a stopped state
either through the core's an_ac_pm_thread_stop inputs or through latches on the bcfg scan ring.
6. Scan configuration latches (bcfg and dcfg scan rings) with alternate initial values as needed. See the
appropriate chip level information regarding configuration ring initialization procedures.
7. Start all core clocks.
8. Once functional clocks are started, circuitry within the A2 core controls initialization of the I-ERAT and D-
ERAT array entries required for first instruction fetch.
9. A thread is released from a stopped state and begins fetching instructions from the starting reset vector.
Threads can be held in a stopped state after reset through several methods:
a. The THRCTL[Tx_Stop] bits can be configured to be active, thereby holding the threads in a quiesced
state when clocks are started. The boot configuration ring (bcfg) is used in step 6 to initialize the
Version 1.3
October 23, 2012
User's Manual
A2 Processor
Initialization
Page 153 of 864