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12.3.2 ERAT Write Entry (eratwe)
Software must use the eratwe instruction to write entries into either ERAT. The eratwe instruction relies on
the MMUCR0[TLBSEL] to determine on which hardware ERAT structure (I-ERAT or D-ERAT) the instruction
operates.
This instruction is embedded hypervisor privileged. This instruction can be executed in either MMU mode or
ERAT-only mode (CCR2[NOTLB] = don't care). The instruction format and details follow.
eratwe
RS,RA,WS
31
RS
RA
0
6
11
IF MMUCR0[TLBSEL] = 0 or 1 (reserved settings) THEN
illegal instruction exception
ELSE IF MMUCR0[TLBSEL] = 2 THEN
If MMUCR1.IRRE = 1 then
entry
I-ERAT LRU round-robin pointer
mark + 1)]
else
entry
If WS = 0 then
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS0
I-ERAT
WS1
else if WS = 1 then
I-ERAT.RPNREG
else if WS = 3 then
I-ERAT.LRU-Watermark-
ELSE IF MMUCR0[TLBSEL] = 3 THEN
If MMUCR1[DRRE] = 1 then
entry
D-ERAT LRU round-robin pointer
mark + 1)]
else
entry
If WS = 0 then
D-ERAT
WS0
D-ERAT
WS0
D-ERAT
WS0
D-ERAT
WS0
Version 1.3
October 23, 2012
WS
211
/
16
21
31
I-ERAT LRU round-robin pointer
RA
60:63
[(entry)]
EPN
(RS
.
0:51
[(entry)]
CLASS
(MMUCR0[TID
.
[(entry)]
V, X
(RS
.
54:55
[(entry)]
TSIZE
convert_to_3bits(RS
.
[(entry)].THDID
(MMUCR0[TID
[(entry)].TGS
(MMUCR0[TGS])
[(entry)].TS
(MMUCR0[TS])
[(entry)].TID
(MMUCR0[TID
[(entry)].TID_NZ
(MMUCR0[TID_NZ])
[(entry)].EXTCLASS
[(entry)]
(I-ERAT.RPNREG)
(RS)
(RS
60:63
D-ERAT LRU round-robin pointer
RA
59:63
[(entry)]
EPN
(RS
.
0:51
[(entry)]
CLASS
(MMUCR0[TID
.
[(entry)]
V, X
(RS
.
54:55
[(entry)]
TSIZE
convert_to_3bits(RS
.
[(I-ERAT LRU round-robin pointer + 1) mod (water-
)
]) when MMUCR1[ICTID] = 1 else (RS
50:51
)
)
56:59
]) when MMUCR1[ITTID] = 1 else (RS
52:55
])
56:63
(MMUCR0[ECL])
)
[(D-ERAT LRU round-robin pointer + 1) mod (water-
)
]) when MMUCR1[DCTID] = 1 else (RS
50:51
)
)
56:59
User's Manual
A2 Processor
52:53
60:63
52:53
Implementation Dependent Instructions
Page 499 of 864
)
)
)
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