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User's Manual
A2 Processor
The TLB is parity protected against soft errors. The details of parity checking are described in the following
sections.
6.1.1 Support for Power ISA MMU Architecture
The A2 memory management unit is based on Power ISA Book III-E Embedded MMU Architecture Version
2.0 (MAV 2.0). Unless otherwise noted, the A2 MMU conforms to this architecture and the following additional
categories: Embedded.Hypervisor (E.HV), Embedded.Hypervisor.LRAT (E.HV.LRAT), Embedded.TLB Write
Conditional (E.TWC), and Embedded.Page Table (E.PT).
Extensions
The Power ISA defines specific requirements for MMU implementations, but also leaves the details of several
features implementation-dependent. The A2 core is fully compliant with the required MMU mechanisms
defined by the Power ISA, but a few optional mechanisms are not supported. These are:
• Page Sizes
The Power ISA for MAV 2.0 defines 32 different page sizes, but does not require that an implementation
support all of them. Accordingly, the A2 core supports five of these page sizes, from 4 KB up to 1 GB
(nonconsecutive), as mentioned in MMU Overview on page 185 and as listed in Table 6-1 Page Size and
Effective Address to EPN Comparison on page 191. The Power ISA page sizes are defined as power of 2
1 KB sizes and represented by a 5-bit value. The page sizes supported by A2 all happen to be power of
4 1 KB sizes. For this reason, the LSB of the architected page size encoding is assumed to be zero
always and is not implemented in the A2 MMU.
• Address Space
The A2 effective page number (EPN) field varies from 34 to 52 bits, depending on page size. The real
page number (RPN) field varies from 12 to 30 bits, depending on page size. The total 42 bits of the real
address is the combination of the RPN with the page offset portion of the effective address. See Address
Translation on page 191 for a more detailed explanation of these fields and the formation of the real
address.
6.2 Page Identification
The TLB is the hardware resource that controls page identification and address translation; it contains page
protection and storage attributes. The Valid (V), Effective Page Number (EPN), Translation Guest Space
identifier (TGS), Translation Logical Partition identifier (TLPID), Translation Space identifier (TS), Translation
ID (TID), and Page Size (SIZE) fields of a particular TLB entry identify the page associated with that TLB
entry. In addition, the indirect (IND) bit of a TLB entry identifies it as a direct virtual to real translation entry
(IND = 0) or an indirect (IND = 1) hardware page table pointer entry that requires additional processing.
Except as noted, all comparisons using these fields must succeed to validate this entry for subsequent trans-
lation and access control processing. Failure to locate a matching direct or indirect TLB entry based on this
criteria for instruction fetches causes a TLB miss exception that results in an instruction TLB error interrupt.
Failure to locate a matching direct or indirect TLB entry based on this criteria for data storage accesses
causes a TLB miss exception that might result in a data TLB error interrupt, depending on the type of data
storage access (certain cache management instructions do not result in an interrupt if they cause an excep-
tion; they simply result in a no-op).
Memory Management
Page 186 of 864
Version 1.3
October 23, 2012
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