IBM A2 User Manual page 522

User's Manual
A2 Processor
Register Short Name:
Decimal SPR Number:
Initial Value:
Slow SPR:
Guest Supervisor Mapping:
Bits Field Name
0:31 ///
32:63 CT
Programming Notes:
1. When any bit for a regular coprocessor type (CT) is set to 1, the bit position for the broadcast CT must
also be set to 1 to enable the broadcast coprocessor type; otherwise, any request that specifies the
broadcast CT fails.
2. Before an mtspr to HACOP, the program must issue sync with L = 0 (also known as a heavyweight sync)
or otherwise ensure that there are no icswx instructions that have not yet completed.
3. A process without hypervisor privilege causes a DSI on issue of the icswx instruction when bit position
CT in HACOP is zero.
Implementation Dependent Instructions
Page 522 of 864
HACOP
351
0x0000000000000000
N
Initial
Value
0x0 Reserved
0x0 Coprocessor Type
Indicates the available coprocessor types for the icswx instruction. Bit n of the register indi-
cates availability of coproccessor type n.
0 Coprocessor unavailable. Accesses generate an unavailable coprocessor type of
data storage interrupt.
1 Coprocessor available.
Read Access:
Write Access:
Duplicated for Multithread:
Notes:
Scan Ring:
Description
Priv
Hypv
Y
HM
func
Version 1.3
October 23, 2012