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User's Manual
A2 Processor
10.4.5 Branch Taken (BRT) Debug Event
BRT debug events occur when BRT debug events are enabled (DBCR0[BRT] = 1), debug interrupts are
enabled (MSR[DE] = 1), and execution is attempted of a branch instruction for which the branch conditions
are satisfied, such that the instruction stream is redirected to the target address of the branch.
When operating in external (DBCR0[EDM] = 1) debug mode, the occurrence of a BRT debug event is
recorded in DBSR[BRT]. In external debug mode, the setting of PCCR0[DBA] determines the resulting debug
actions. If the debug action is a stop, the processor enters the stop state and ceases the processing of
instructions. The program counter contains the address of the branch instruction that caused the BRT debug
event. If the PCCR0[DBA] decode does not stop the processor, instruction execution continues, and any
additional debug actions are determined by the setting of DBCR0[IDM] as described below.
When operating in internal debug mode (DBCR0[IDM] = 1) with debug interrupts enabled (MSR[DE] = 1), the
occurrence of a BRT debug event is recorded in DBSR[BRT] and causes the instruction execution to be
suppressed. A debug interrupt occurs with CSRR0 set to the address of the branch instruction that caused
the BRT debug event.
When debug interrupts are disabled (MSR[DE] = 0), BRT debug events cannot occur. Because taken
branches are a very common operation and thus likely to be frequently executed within the critical class inter-
rupt handlers (which typically have MSR[DE] set to 0), allowing BRT debug events under these conditions
would lead to an undesirable number of delayed (and hence imprecise) debug interrupts.
10.4.6 Trap (TRAP) Debug Event
TRAP debug events occur when TRAP debug events are enabled (DBCR0[TRAP] = 1) and execution is
attempted of a trap (tw, twi, td, tdi) instruction for which the trap condition is satisfied.
When enabled, the occurrence of a TRAP debug event is recorded in DBSR[TRAP]. If debug interrupts are
not enabled (MSR[DE] = 0), the imprecise debug event (DBSR[IDE]) bit is also set. The resulting actions
taken by the processor due to the TRAP debug event depend on the specific debug configuration.
When operating in external debug mode (DBCR0[EDM] = 1), the setting of PCCR0[DBA] determines the
resulting debug actions. If the debug action is a stop, the processor enters the stop state and ceases the
processing of instructions. The program counter contains the address of the trap instruction that caused the
TRAP debug event. If the PCCR0[DBA] decode does not stop the processor, instruction execution continues,
and any additional debug actions are determined by the setting of DBCR0[IDM].
When operating in internal debug mode (DBCR0[IDM] = 1) with debug interrupts enabled (MSR[DE] = 1), a
debug interrupt occurs with CSRR0 set to the address of the trap instruction that caused the TRAP debug
event. When operating in internal debug mode with debug interrupts disabled (MSR[DE] = 0), the debug
interrupt does not occur immediately. Instruction execution is suppressed and a trap exception type of
program interrupt occurs instead. A debug interrupt also occurs later, if and when MSR[DE] is set to 1. This
enables debug interrupts, assuming software has not cleared the TRAP debug event status from the DBSR in
the meantime. Upon such a "delayed" interrupt, the debug interrupt handler software can query the
DBSR[IDE] field to determine that the debug interrupt has occurred imprecisely.
10.4.7 Return (RET) Debug Event
RET debug events occur when RET debug events are enabled (DBCR0[RET] = 1) and execution is
attempted of a noncritical class return (rfi) instruction.
Debug Facilities
Version 1.3
Page 412 of 864
October 23, 2012
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