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User's Manual
A2 Processor
load single instruction, it is converted to double format and placed in the target FPR. Conversely, a floating-
point value stored from an FPR into storage using a store single instruction is converted to single format
before being placed in storage.
The lengths of the exponent and the fraction fields differ between these two formats. The structure of the
single and double formats are shown in Table 3-5 and Table 3-6, respectively.
Table 3-5. Floating-Point Single Format
S
EXP
0
1
9
Table 3-6. Floating-Point Double Format
S
EXP
0
1
12
Values in floating-point format are composed of three fields:
Table 3-7. Format Fields
Field
S
Sign bit
EXP
Exponent + bias
FRACTION
Fraction
If only a portion of a floating-point data item in storage is accessed, such as with a load or store instruction for
a byte or halfword (or word in the case of floating-point double format), the value affected depends on
whether the Power ISA embedded system is operating with big-endian or little-endian byte ordering.
3.4.1 Value Representation
Representation of numeric values in the floating-point formats consists of a sign bit (S), a biased exponent
(EXP), and the fraction portion (FRACTION) of the significand. The significand consists of a leading implied
bit concatenated on the right with the FRACTION. This leading implied bit is 1 for normalized numbers and 0
for denormalized numbers and is located in the unit bit position (that is, the first bit to the left of the binary
point). Values representable within the two floating-point formats can be specified by the parameters listed in
Table 3-8.
Table 3-8. IEEE 754 Floating-Point Fields
Exponent Bias
Maximum Exponent
Minimum Exponent
Field Widths (Bits)
Sign
FU Programming Model
Page 134 of 864
FRACTION
31
(Sheet 1 of 2)
Single
+127
+127
–126
1
FRACTION
63
Description
+1023
+1023
–1022
1
Double
Version 1.3
October 23, 2012
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