Auxiliary Execution Unit (Axu) Port; Jtag Port - IBM A2 User Manual

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User's Manual
A2 Processor
An entity outside the A2 core is expected to be able to queue the S store-type operations and give a pop indi-
cation to the A2 core for each as it is processed and the queue entry is available. For an entity outside the A2
core that also support store gathering, it should give a gather indication to the A2 core when the store is gath-
ered with an existing queue entry to let the A2 core know that an additional queue entry is available.

1.5.2 Auxiliary Execution Unit (AXU) Port

This interface provides the A2 core with the flexibility to attach a tightly-coupled coprocessor-type macro
incorporating instructions that go beyond those provided within the processor core itself. The AXU port
provides sufficient functionality for attachment of various coprocessor functions such as a fully-compliant
Power ISA floating-point unit (single- or double-precision), multimedia engine, DSP, or other custom function
implementing algorithms appropriate for specific system applications. The AXU interface supports can be
used with macros that contain their own register files. AXU load and store instructions can directly access the
A2 core data cache, with operands of up to a double quadword (32 bytes) in length.
The AXU interface provides the capability for a coprocessor to execute instructions that are not part of the
Power ISA instruction set at the same time that the A2 core is executing PowerISA instructions. Areas within
the architected instruction space allow for these customer-specific or application-specific AXU instruction set
extentions. Further description is beyond the scope of this document.

1.5.3 JTAG Port

The A2 core SCOM port supports the indirect attachment of a debug tool such as the RISCWatch product
from IBM. A logic block outside the A2 core must provide JTAG to SCOM port translation. Through the SCOM
port, and using the debug facilities designed into the A2 core, a debug workstation can single-step the
processor and interrogate the internal processor state to facilitate hardware and software debugging.
Version 1.3
Overview
October 23, 2012
Page 59 of 864

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