Debug Control Register 1 (Dbcr1); Figure 8-2. Debug Control Register 1 (Dbcr1) - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
IAC 2 Debug Event
0 Disable IAC 2 debug event.
9 IAC2
1 Enable IAC 2 debug event.
IAC 3 Debug Event
0 Disable IAC 3 debug event.
10 IAC3
1 Enable IAC 3 debug event.
IAC 4 Debug Event
11 IAC4 0 Disable IAC 4 debug event.
1 Enable IAC 4 debug event.
Data Address Compare (DAC) 1 Read Debug Event
0 Disable DAC 1 read debug event.
12 DAC1R
1 Enable DAC 1 read debug event.
DAC 1 Write Debug Event
0 Disable DAC 1 write debug event.
13 DAC1W
1 Enable DAC 1 write debug event.
DAC 2 Read Debug Event
14 DAC2R 0 Disable DAC 2 read debug event.
1 Enable DAC 2 read debug event.
DAC 2 Write Debug Event
0 Disable DAC 2 write debug event.
15 DAC2W
1 Enable DAC 2 write debug event.
Return Debug Event
0 Disable return (rfi/rfci/rfmci) debug event.
16 RET
1 Enable return (rfi/rfci/rfmci) debug event.
17:30 Reserved
Freeze timers on debug event
0 Timers are not frozen.
31 FT
1 Freeze timers if a DBSR field associated with a debug event
is set.

8.6.2 Debug Control Register 1 (DBCR1)

DBCR1 is an SPR that is used to configure IAC debug events. DBCR1 can be written from a GPR using
mtspr , and can be read into a GPR using mfspr .
IAC1US
IAC2US
0 1 2 3 4 5 6 7 8 9 10
IAC1ER
IAC2ER

Figure 8-2. Debug Control Register 1 (DBCR1)

Instruction Address Compare (IAC) 1 User/Super-
visor
00 Both
0:1 IAC1US
01 Reserved
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
Page 240 of 589
IAC12M
14 15 16 17 18 19 20 21 22 23 24 25 26
IAC12AT
rfci/rfmci does not cause a return
debug event if MSR[DE] = 0 in internal
debug mode, unless also in external
debug mode or debug wait mode.
IAC4US
IAC3US
IAC3ER
IAC4ER
Preliminary
IAC34M
30 31
IAC34AT
debug.fm.
September 12, 2002