Debug Control Register 2 (Dbcr2); Figure 8-3. Debug Control Register 2 (Dbcr2) - IBM PPC440X5 CPU Core User Manual

Preliminary

8.6.3 Debug Control Register 2 (DBCR2)

DBCR2 is an SPR that is used to configure DAC and DVC debug events. DBCR2 can be written from a GPR
using mtspr , and can be read into a GPR using mfspr .
DAC2US
DAC1US
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DAC1ER DAC2ER

Figure 8-3. Debug Control Register 2 (DBCR2)

Data Address Compare (DAC) 1 User/Supervisor
00 Both
01 Reserved
0:1 DAC1US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
DAC 1 Effective/Real
00 Effective (MSR[DS] = don't care)
01 Reserved
2:3 DAC1ER
10 Virtual (MSR[DS] = 0)
11 Virtual (MSR[DS] = 1)
DAC 2 User/Supervisor
00 Both
01 Reserved
4:5 DAC2US
10 Supervisor only (MSR[PR] = 0)
11 User only (MSR[PR] = 1)
DAC 2 Effective/Real
00 Effective (MSR[DS] = don't care)
01 Reserved
6:7 DAC2ER
10 Virtual (MSR[DS] = 0)
11 Virtual (MSR[DS] = 1)
DAC 1/2 Mode
00 Exact match
01 Address bit mask
8:9 DAC12M
10 Range inclusive
11 Range exclusive
DAC 1/2 Asynchronous
0 Debug interrupt caused by DAC1/2 exception
10 DAC12A
1 Debug interrupt caused by DAC1/2 exception
11 Reserved
Data Value Compare (DVC) 1 Mode
00 Reserved
01 AND all bytes enabled by DVC1BE
12:13 DVC1M
10 OR all bytes enabled by DVC1BE
11 AND-OR pairs of bytes enabled by DVC1BE
debug.fm.
September 12, 2002
DAC12M
DVC1M
DAC12A DVC2M
will be synchronous
will be asynchronous
DVC1BE
19 20 23 24
Match if address[0:31] = DAC 1/2[0:31]; two inde-
pendent compares
Match if address = DAC1; only compare bits cor-
responding to 1 bits in DAC2
Match if DAC1 address < DAC2
Match if address < DAC1 OR address
(0 AND 1) OR (2 AND 3)
User's Manual
PPC440x5 CPU Core
27 28 31
DVC2BE
DAC2
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