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Analog-to-Digital Converter/Brownout Detector
2.2.2.5 Power Configuration Register (PC)
In this register, the clock divider bits are programmed to set the system clock frequency for
analog operation. Program bits [3:0] to the number of conversions necessary, depending
on the conversion. Bit [4] can be used as an enable for external I/O pads. If this bit is set
to 1, the Battery Control Logic Pin (BATCNTL) will be a valid output. If an external battery
measurement circuit is not used, this bit should be set to 0.
NOTE: Allow two A2DCLK cycles between successive write cycles to this register. Otherwise, ADC behavior
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:15
14:11
10:8
2-16
can become erratic.
31
30
29
28
27
0
0
0
0
RO
RO
RO
RO
RO
15
14
13
12
11
BATLOC
0
0
0
0
RO
RW
RW
RW
RW
NAME
///
Reserved Reading returns 0. Write the reset value.
Battery Measurement Location
Channel number corresponding to the location programmed into the
HW:INP field for battery measurement. When PC:BATLOC = HW:INP,
the output pin BATCNTL goes HIGH. At all other times, the BATCNTL
BATLOC
pin is LOW.
To disable toggling the BATCNTL pin, program these bits to a value
that will never appear in HW:INP, for example 0b1111.
Clock Select If the nominal value is used, the only valid settings are
011, 100, 101, and 110.
000 = Clock oscillator (nominally 10 to 20 MHz)
001 = Clock oscillator /2
010 = Clock oscillator /4
CLKSEL
011 = Clock oscillator /8
100 = Clock oscillator /16
101 = Clock oscillator /32
110 = Clock oscillator /64
111 = Clock oscillator /128
Table 2-11. PC Register
26
25
24
23
///
0
0
0
0
0
RO
RO
RO
RO
10
9
8
7
CLKSEL
PWM
0
0
0
0
0
RW
RW
RW
RW
0xFFFC3000 + 0x10
Table 2-12. PC Fields
DESCRIPTION
Version 1.0
LH79524/LH79525 User's Guide
22
21
20
19
18
0
0
0
0
0
RO
RO
RO
RO
RO
6
5
4
3
2
0
0
0
0
0
RW
RW
RW
RW
RW
Program this field with the
17
16
0
0
RO
RO
1
0
NOC
0
0
RW
RW
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