Table 17-38. Outcsr2 Register; Table 17-39. Outcsr2 Fields; Control Status Register 2 For Out Ep1 And Ep 2 (Outcsr2) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

17.2.3.8 Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2)

OUTCSR2 provides further control bits for transfers through the currently-selected OUT
endpoint
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:8
7
6
5
4
3:0
.

Table 17-38. OUTCSR2 Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
///
0 0 0 0
RO RO RO RO RO

Table 17-39. OUTCSR2 Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Auto Clear This bit allows OUT_PKT_RDY to be automatically cleared
if it equals OUTMAXP. If the packet is smaller than OUTMAXP, software
must manually clear OUT_PKT_RDY.
1 = OUT_PKT_RDY is automatically programmed to 0, without any
AUTO_CLR
intervention from software, each time a complete packet is read from
OUT FIFO
0 = Software must explicitly clear the OUT_PKT_RDY bit after reading
each packet
Isochronous Enable Use this bit to enable the OUT endpoint for
isochronous transfers or to enable the OUT endpoint for bulk or interrupt
transfers.
ISO
1 = Enable the OUT endpoint for isochronous transfers
0 = Enable the OUT endpoint for bulk or interrupt transfers
USB DMA Enable Use this bit to enable DMA bulk transfers for the
OUT endpoint.
USB_DMA_EN
1 = The OUT FIFO is accessed via the DMA
0 = The OUT FIFO is accessed via direct Reads
DMA Operation Mode There are two modes of DMA operation.
1 = A DMA request (but no interrupt) is generated for OUT packets of
DMA_MODE
size OUTMAXP bytes, and an interrupt is generated (but no DMA
request) for all other size packets
0 = A DMA request and interrupt is generated for all OUT packets
/// Reserved Reading returns 0. Write the reset value.
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
0 0 0 0 0
RO RO RO RW
0xFFFF5000 + 0x054
(with the INDEX register set to 1 or 2)
FUNCTION
Version 1.0
Universal Serial Bus Device
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW R R
17 16
0 0
RO RO
1 0
///
0 0
R R
17-29