Table 2-2. Hw Register; Table 2-3. Hw Fields; Register Descriptions - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

2.2.2 Register Descriptions

2.2.2.1 High Word Register (HW)
HW is the High Word Register. This Read Only status register shows the contents of the
current conversion's high word in the control bank. There is a one-to-one correspondence
between the contents of the control bank high word and the contents of this register for the
current conversion in progress.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:7 SETTIME
6:3
2
1:0
31 30 29 28 27
0 0 0 0 0
RO RO RO RO RO
15 14 13 12 11
SETTIME
0 0 0 0 0
RO RO RO RO RO
NAME
/// Reserved Reading returns 0. Write the reset value.
Number of Clock Cycles Specifies the number of clock cycles that the ADC
allows for the input signal to settle to within required accuracy before beginning
conversion. Used with bits [10:8] of the PC Register to set the acquire time in
clock cycles (see Section 2.2.2.5).
For example, if Frequency In (ƒIN) = 2 MHz (500 ns period):
PC[10:8] = 010 (i.e., divide ƒIN by 4)
HW[15:6] = 000100000 (i.e., 32 cycles)
Therefore, acquire time is 500 ns × 4 × 32 = 64 μs
In+ Mux Determines the signal connected to the positive input of the ADC.
INP
See Table 2-4.
In- Mux Determines the signal connected to the negative input of the ADC.
INM
1 = GND
0 = Ref- (output of the Ref- Mux)
Ref+ Mux Determines the signal connected to the positive reference of the ADC.
00 = VREF+ (positive terminal of the internal bandgap reference)
REFP
01 = AN0 (UL/X+)
10 = AN2 (LL/ Y+)
11 = AN8
Analog-to-Digital Converter/Brownout Detector

Table 2-2. HW Register

26 25 24 23
///
0 0 0 0
RO RO RO RO
10 9 8 7
0 0 0 0
RO RO RO RO
0xFFFC3000 + 0x00

Table 2-3. HW Fields

DESCRIPTION
Version 1.0
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
INP INM
0 0 0 0 0
RO RO RO RO RO
17 16
0 0
RO RO
1 0
REFP
0 0
RO RO
2-11