Table 6-12. Txstatus Register; Table 6-13. Txstatus Fields; Transmit Status Register (Txstatus) - Sharp LH79524 User Manual

LH79524/LH79525 User's Guide

6.3.2.4 Transmit Status Register (TXSTATUS)

This register provides transmit status details. Individual bits may be cleared by writing 1 to
them. It is not possible to program a bit to 1 by writing to the register.
BIT
FIELD
RESET
TYPE
BIT
FIELD
RESET
TYPE
ADDR
BITS
31:7
6
5

Table 6-12. TXSTATUS Register

31 30 29 28
0 0 0 0
RO RO RO RO RO
15 14 13 12
0 0 0 0
RO RO RO RO RO

Table 6-13. TXSTATUS Fields

NAME
/// Reserved Reading returns 0. Write the reset value.
Transmit Underrun This bit shows when transmit DMA was not able
to read data from the buffer in system memory. The cause can be that
the AHB or ASB bus was not granted in time, a 'Not OK' response was
returned, a zero length buffer was read, or because a Used bit was read
midway through frame transmission. If this happens, the transmitter forc-
es a bad CRC and the Transmit Error (ETHERTXER) pin HIGH.
TXUNDER
Read:
1 = DMA Unable to read data from memory
0 = Normal operation
Write:
1 = Reset bit to 0
0 = No effect
Transmit Complete Advises when a frame has been transmitted.
Read:
1 = Frame transmission complete
TXCOMPLETE 0 = Frame transmission not complete
Write:
1 = Reset bit to 0
0 = No effect
27 26 25 24 23
///
0 0 0 0 0
RO RO RO RO
11 10 9 8 7
///
0 0 0 0 0
RO RO RO RO
0xFFFC7000 + 0x14
FUNCTION
Version 1.0
Ethernet MAC Controller
22 21 20 19 18
0 0 0 0 0
RO RO RO RO RO
6 5 4 3 2
0 0 0 0 0
RW RW RW RO RW
17 16
0 0
RO RO
1 0
0 0
RW RW
6-25