Table 4-12. Usable Minimum Values Affecting Stn Back Porch Width; Lcd Vertical Timing Signals - Sharp LH79524 User Manual

Color Liquid Crystal Display Controller
4.3.8.1.1 STN Horizontal Timing Restrictions
The CLCDC's dedicated DMA system requests new data at the start of each horizontal dis-
play line. Time must be allowed for the DMA transfer operation to occur. Time must also
be allowed for the data to propagate down the FIFO path within the LCD interface. These
delays constitute LCD data path latency. The data path latency imposes some restrictions
on the usable minimum values for horizontal back porch width when operating in the STN
modes. The value restrictions are listed in Table 4-12.
NOTE: The minimum value for PCD is 4.

4.3.8.2 LCD Vertical Timing Signals

Data is written to an LCD panel in frames. Each frame is composed of a number of hori-
zontal lines. The vertical components of LCD timing describe the process of writing one full
frame to an LCD panel.
Each frame begins with a frame pulse or vertical synchronization pulse of programmable
duration. Each frame pulse is followed by a programmable delay, the vertical back porch.
When the vertical back porch expires, all line information for the frame is presented to the
LCD panel. See Section 4.3.8.1. The line information is followed by another programmable
delay, the vertical front porch.
In STN mode, the vertical front porch, pulse width, and vertical back porch are
not programmable.
4-14

Table 4-12. Usable Minimum Values Affecting STN Back Porch Width

HORIZONTAL TIMING VALUE SINGLE-PANEL MODE DUAL-PANEL MODE
TIMING0:HSW
TIMING0:HBP
TIMING0:HFP
TIMING2:PCD
3
5
5
1 × (CLCD CLOCK/3)
Version 1.0
LH79524/LH79525 User's Guide
3
5
5
5 × (CLCD CLOCK/7)